公开(公告)号：WO1981001894A1

公开(公告)日：1981-07-09

申请号：PCT/US1980001666

申请日：1980-12-10

Applicant: NCR CORP

Inventor： NCR CORP ,  SCHMIDT C

IPC: G06F13/00

CPC classification number: G06F12/0864 ,  G06F2212/601

Abstract: Increasing the speed and hit ratio for data fetches in data processing systems is essential. Increased data fetch speed normally results from using a fast cache memory with a slower main memory. The hit ratio for such fetches can be increased by using cache memory (26') which incorporates data buffer (34') that stores blocks of data that are varied in size and a set associative memory as index (32') which stores block addresses for main memory (14), which addresses are associated with the data blocks stored in buffer (34'). The block sizes are varied by selectively inhibiting address bits provided to an input (40') of the index (32') by address inhibit circuit (54) in response to information stored in block size register (54). Such block size information is also provided to a fetch generate counter (60') and a fetch return counter (62') for controlling the number of words transferred as a block from main memory (14) to cache memory (26').

Abstract translation: 提高数据处理系统中数据读取的速度和命中率至关重要。 增加的数据获取速度通常是由于使用较慢主存储器的快速缓存。 这种提取的命中率可以通过使用高速缓冲存储器（26'）来增加，缓存存储器（26'）包含存储大小变化的数据块的数据缓冲器（34'）和作为存储块地址的索引（32'）的集合关联存储器 对于主存储器（14），哪个地址与存储在缓冲器（34'）中的数据块相关联。 响应于存储在块大小寄存器（54）中的信息，通过选择性地禁止由地址禁止电路（54）提供给索引（32'）的输入（40'）的地址位来改变块大小。 这样的块大小信息还被提供给获取生成计数器（60'）和用于将从块存储器传送的字的数量从主存储器（14）控制到高速缓存存储器（26'）的获取返回计数器（62'）。