公开(公告)号：WO1982001607A1

公开(公告)日：1982-05-13

申请号：PCT/US1981001396

申请日：1981-10-16

Applicant: NCR CORP

Inventor： NCR CORP ,  SCHUCK DAVID B

IPC: G06F13/00

CPC classification number: G06F13/4072 ,  G06F13/4217

Abstract: In order to provide fast data transfers and to ensure that the capacitive loading remains fixed, a data communication bus structure for interconnecting a desired number of subsystems of a data processing system comprises an integrated circuit (1) having bus conductors (50, 60, 70) of fixed length and a fixed number of ports (10, 20, 30) for connecting the subsystems. Each port comprises the control and data terminals for a group of driver/receiver circuits (11-13, 21-23, 31-33), each driver/receiver circuit of a group being connected to a respective bus conductor. Each driver/receiver circuit comprises a driver circuit having address and data output latches and driver gates, and a receiver circuit having address and data input latches.

Abstract translation: 为了提供快速数据传输并且确保电容性负载保持固定，用于互连数据处理系统的期望数量的子系统的数据通信总线结构包括具有总线导体（50,60,70）的集成电路（1） ）和固定数量的端口（10,20,30），用于连接子系统。 每个端口包括用于一组驱动器/接收器电路（11-13,21-23,31-33）的控制和数据端子，一组的每个驱动器/接收器电路连接到相应的总线导体。 每个驱动器/接收器电路包括具有地址和数据输出锁存器和驱动器门的驱动器电路，以及具有地址和数据输入锁存器的接收器电路。