公开(公告)号：WO1982002266A1

公开(公告)日：1982-07-08

申请号：PCT/US1981001733

申请日：1981-12-21

Applicant: NCR CORP

Inventor： NCR CORP ,  EDWARDS GORDON LEE JR ,  SMITH WALTER ANDREW

IPC: G06F11/10

CPC classification number: G06F11/1012

Abstract: Error detecting and correcting system which is simple, inexpensive and low in demands on memory capacity and memory cycle time. A memory for storing data includes a first section, the data being stored in the first section in rows and columns and first means for storing first check bits for the rows of data. Error correcting means (22) includes: means for generating check bits (62) for the columns of data so as to produce a check word for a predetermined number of the rows of data; a second memory section (26-3) for storing at least one check word; and processor means operatively coupling the generating means with said first and second sections to enable the error correcting means to utilize the first check bits to locate a row of data in which at least one bit is in error and also to enable the error correcting means to utilize the associated check word to correct any errors which exist in the row of data.

Abstract translation: 误差检测和校正系统，其对于存储器容量和存储器周期时间的要求是简单，便宜和低的。 用于存储数据的存储器包括第一部分，数据以行和列存储在第一部分中，第一装置用于存储数据行的第一校验位。 误差校正装置（22）包括：用于产生数据列的校验位（62）的装置，以产生预定数量的数据行的校验字; 用于存储至少一个校验字的第二存储器部分（26-3）; 并且处理器装置可操作地将生成装置与所述第一和第二部分耦合，以使得纠错装置能够利用第一校验位来定位其中至少一个位是错误的数据行，并且还使纠错装置能够 利用关联的检查词来纠正数据行中存在的任何错误。

公开(公告)号：EP0067864A4

公开(公告)日：1986-02-13

申请号：EP82900486

申请日：1981-12-21

Applicant: NCR CORP

Inventor： EDWARDS GORDON LEE JR ,  SMITH WALTER ANDREW

IPC: G11C29/00 ,  G06F11/10 ,  G11C29/42

CPC classification number: G06F11/1012

Abstract: An error detecting and correcting system, comprising: a memory for storing data including a first section, the data being stored in the first section in rows and columns; first means for storing first check bits for the rows of data; and error correcting means, including: means for generating check bits for the columns of data so as to produce a check word for a predetermined number of the rows of data; a second section for storing at least one check word; and processor means operatively coupling the generating means with said first and second sections to enable the error correcting means to utilize the first check bits to locate a row of data in which at least one bit is in error and also to enable the error correcting means to utilize said check word to correct any errors which exist in the row of data. The method of this invention utilizes the first check bits which relate to the rows of data to detect a particular row in which an error occurs, and also utilizes the associated check word for correcting any error which exists in said particular row.