公开(公告)号：JP2002149731A

公开(公告)日：2002-05-24

申请号：JP2000345719

申请日：2000-11-13

Applicant: NEW IND RES ORGANIZATION

Inventor： NUMA MASAHIRO ,  YAMAMOTO HIROSUKE

IPC: G01R31/3183 ,  G01R31/28 ,  G01R31/319 ,  G06F17/50

Abstract: PROBLEM TO BE SOLVED: To speedily find an error place of a logic circuit which has a design error and to obtain a circuit which has been rectified in a short time. SOLUTION: The object logic circuit is converted into a combinational circuit having truth tables as elements through a circuit conversion step (#1-1) and device conversion step (#1-2), and combined candidates for truth tables to be rectified are previously extracted through extraction steps (#1-3 to #5) based upon an index representing the possibility that the external output value of the logic circuit to a specific input pattern is varied for each truth table according to its contents alterations and a simulation for evaluating the external output value of the logic circuit by using six values of 0, 1, X, X', D, and E; and the combined candidates of the truth value are further narrowed down (#5-1) under conditions where a necessary number of truth table variables are assigned to represent the external output value by a logical function and function specifications should be satisfied, and a rectification step (#6-1) is applied to the combination of the narrowed-down truth tables.