CONTROL AND SLOW DATA TRANSMISSION METHOD FOR SERIAL INTERFACE
    1.
    发明申请
    CONTROL AND SLOW DATA TRANSMISSION METHOD FOR SERIAL INTERFACE 审中-公开
    用于串行接口的控制和慢速数据传输方法

    公开(公告)号:WO2008065515A2

    公开(公告)日:2008-06-05

    申请号:PCT/IB2007003665

    申请日:2007-11-28

    CPC classification number: H04L25/028 H04L25/0272 H04L25/0292

    Abstract: A scalable low voltage signaling (SLVS) serial interface structure is configured as a 0.4V NMOS totem-pole driver structure for both high speed differential signaling and slow speed single-ended signaling using the same 0.4V NMOS totem-pole driver structure. An un-terminated receiver (Rx) and a CMOS inverter comparator powered from a 0.4 volt supply, is used for receiving the slow speed single-ended 0 - 100 mega bits per second (Mbps) signaling in a data link. A terminated receiver (Rx) and a differential comparator powered from a 0.4 volt supply, is used for receiving the high speed differential 2 giga bits per second (Gbps) signaling in the data link.

    Abstract translation: 可扩展的低电压信号(SLVS)串行接口结构被配置为0.4V NMOS图腾柱驱动器结构,用于高速差分信号和使用相同的0.4V NMOS图腾柱驱动器结构的低速单端信号。 使用未端接的接收器(Rx)和由0.4伏电源供电的CMOS反相器比较器,用于接收数据链路中的慢速单端0 - 100兆位(Mbps)信号。 端接的接收器(Rx)和由0.4伏电源供电的差分比较器用于接收数据链路中每秒高达2G比特(Gbps)的信号。

    SYSTEM AND METHOD FOR PRE-DEFINED WAKE-UP OF HIGH SPEED SERIAL LINK
    2.
    发明申请
    SYSTEM AND METHOD FOR PRE-DEFINED WAKE-UP OF HIGH SPEED SERIAL LINK 审中-公开
    用于高速串行链路的预定义唤醒的系统和方法

    公开(公告)号:WO2008032163A3

    公开(公告)日:2008-05-29

    申请号:PCT/IB2007002579

    申请日:2007-09-07

    Abstract: A system and method for transmitting and receiving through a high speed serial link with power up and power down capability. The exemplary embodiments of this invention involves a method of power up and power down the high-speed serial link without using high voltage swing control and signaling. Both the transmitter and the receiver wake up only during pre-defined burst cycles. During each burst cycle, data will be transmitted and received in burst mode. Outside each burst cycle, the transmitter and receiver will be powered off or partially powered off. Various phase-locked loop based circuit ensure the transmitter and the receiver can be locked in frequency and phase quickly at the time of power-up. The duration of the burst cycle and the interval between two adjacent burst cycles can be either fixed or changed by upper level protocol.

    Abstract translation: 一种通过具有上电和断电能力的高速串行链路进行发送和接收的系统和方法。 本发明的示例性实施例涉及一种在不使用高电压摆动控制和信令的情况下上电和断电高速串行链路的方法。 发送器和接收器都只在预定义的突发周期中唤醒。 在每个突发周期中,数据将以突发模式发送和接收。 在每个突发周期之外,发射机和接收机将断电或部分断电。 各种基于锁相环的电路确保发射机和接收机在上电时能够快速锁定频率和相位。 突发周期的持续时间和两个相邻突发周期之间的间隔可以是固定的,也可以是上层协议所改变的。

    A COAXIAL CABLE AND A MANUFACTURING METHOD

    公开(公告)号:AU2002256745A1

    公开(公告)日:2003-12-19

    申请号:AU2002256745

    申请日:2002-06-04

    Applicant: NOKIA CORP

    Abstract: The invention relates to a coaxial cable for transmitting signals, comprising an inner conductor (302), said inner conductor (302) comprising a conducting layer (400) for conducting a signal The conducting layer (400) of the inner conductor (302) has a thickness that depends on the skin factor of the highest frequency component contained in signals to be transmitted in the coaxial cable (300). The invention also relates to a method for manufacturing said coaxial cable.

    SYSTEM AND METHOD FOR PRE-DEFINED WAKE-UP OF HIGH SPEED SERIAL LINK
    4.
    发明公开
    SYSTEM AND METHOD FOR PRE-DEFINED WAKE-UP OF HIGH SPEED SERIAL LINK 审中-公开
    系统和方法,以唤醒PREDEFINED串行高速连接

    公开(公告)号:EP2062362A4

    公开(公告)日:2009-10-14

    申请号:EP07825073

    申请日:2007-09-07

    Abstract: A system and method for transmitting and receiving through a high speed serial link with power up and power down capability. The exemplary embodiments of this invention involves a method of power up and power down the high-speed serial link without using high voltage swing control and signaling. Both the transmitter and the receiver wake up only during pre-defined burst cycles. During each burst cycle, data will be transmitted and received in burst mode. Outside each burst cycle, the transmitter and receiver will be powered off or partially powered off. Various phase-locked loop based circuit ensure the transmitter and the receiver can be locked in frequency and phase quickly at the time of power-up. The duration of the burst cycle and the interval between two adjacent burst cycles can be either fixed or changed by upper level protocol.

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