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公开(公告)号：US20240402244A1
公开(公告)日：2024-12-05
申请号：US18204601
申请日：2023-06-01
Applicant: NXP B.V.
Inventor： Giorgio Carluccio , Björn Christian Brands , Henrik Asendorf
IPC: G01R31/28
Abstract: A two-stage test process for testing IC packages having integrated launchers includes a first stage in which an RF-accurate test process is used to perform RF-accurate tests on a sample set of IC packages to obtain RF-accurate test results and a loop-back test process is performed to obtain loop-back test results. Test characterization data is obtained by comparing the RF-accurate test results to the loop-back test results. In a second stage, larger-scale testing is performed solely with the loop-back test process, and the loop-back test results for each tested IC package are compared with the test characterization data to characterize the test operation of the tested IC package. The loop-back test process can employ a test jig employing a PCB-mounted or PCB-integrated loop-back structure for relatively rapid test setup and test processing.
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公开(公告)号：US11415626B2
公开(公告)日：2022-08-16
申请号：US17118828
申请日：2020-12-11
Applicant: NXP B.V.
Inventor： Jan-Peter Schat , Abdellatif Zanati , Henrik Asendorf , Maristella Spella , Waqas Hassan Syed , Giorgio Carluccio , Antonius Johannes Matheus de Graauw
IPC: G01R31/311
Abstract: A method of testing a semiconductor device. An apparatus comprising a semiconductor device and a test apparatus. The semiconductor device includes an integrated circuit and a plurality of external radiating elements at a surface of the device, the radiating elements include transmit elements and receive elements. The test apparatus includes a surface for placing against the surface of the device. The test apparatus also includes at least one waveguide, which extends through the test apparatus for routing electromagnetic radiation transmitted by one of the transmit elements of the device to one of the receive elements of the device. Each waveguide comprises a plurality of waveguide openings for coupling electromagnetically to corresponding radiating elements of the plurality of radiating elements located at the surface of the device. A spacing between the waveguide openings of each waveguide is larger than, or smaller than a spacing between the corresponding radiating elements.
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公开(公告)号：US20240154300A1
公开(公告)日：2024-05-09
申请号：US18496975
申请日：2023-10-30
Applicant: NXP B.V.
Inventor： Harshitha Thippur Shivamurthy , Rabia Syeda , Rocío Gabriela Molina Moreno , Cristine Aguila Badiao , Pieter Lok , Adrianus Buijsman , Leo van Gemert , Maarten Lont , Giorgio Carluccio , Antonius Johannes Matheus de Graauw
CPC classification number: H01Q1/38 , H01Q1/2283
Abstract: A system comprising: a waveguide assembly comprising a plurality of waveguides, the plurality of waveguides comprising at least a first waveguide and a second waveguide, and an integrated circuit package, IC package, comprising a plurality of launchers to one or more of transmit signalling to and receive signalling from a respective one of the plurality of waveguides, wherein the waveguide assembly comprises a surface configured to be coupled to the IC package and each of the plurality of waveguides comprises an opening in the surface configured to be aligned with its respective launcher, and wherein each of the openings has a major dimension and a minor dimension, wherein the major dimension is larger than the minor dimension, and wherein the major dimension of at least the opening of the first waveguide is oriented perpendicular to the major dimension of the opening of the second waveguide.
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公开(公告)号：US20220173490A1
公开(公告)日：2022-06-02
申请号：US17106269
申请日：2020-11-30
Applicant: NXP B.V
Inventor： Adrianus Buijsman , Abdellatif Zanati , Giorgio Carluccio
Abstract: A method of manufacturing a device is provided. The method includes forming a first cavity in a first substrate with the first cavity having a first depth. A second cavity is formed in a second substrate with the second cavity having a second depth. The first cavity and the second cavity are aligned with each other. The first substrate is affixed to the second substrate to form a waveguide substrate having a hollow waveguide with a first dimension substantially equal to the first depth plus the second depth. A conductive layer is formed on the sidewalls of the hollow waveguide. The waveguide substrate is placed over a packaged semiconductor device, the hollow waveguide aligned with a launcher of the packaged semiconductor device.
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Patent Agency Ranking
公开(公告)号：US20210239754A1
公开(公告)日：2021-08-05
申请号：US17118828
申请日：2020-12-11
Applicant: NXP B.V.
Inventor： Jan-Peter Schat , Abdellatif Zanati , Henrik Asendorf , Maristella Spella , Waqas Hassan Syed , Giorgio Carluccio , Antonius Johannes Matheus de Graauw
IPC: G01R31/311
Abstract: A method of testing a semiconductor device. An apparatus comprising a semiconductor device and a test apparatus. The semiconductor device includes an integrated circuit and a plurality of external radiating elements at a surface of the device, the radiating elements include transmit elements and receive elements. The test apparatus includes a surface for placing against the surface of the device. The test apparatus also includes at least one waveguide, which extends through the test apparatus for routing electromagnetic radiation transmitted by one of the transmit elements of the device to one of the receive elements of the device. Each waveguide comprises a plurality of waveguide openings for coupling electromagnetically to corresponding radiating elements of the plurality of radiating elements located at the surface of the device. A spacing between the waveguide openings of each waveguide is larger than, or smaller than a spacing between the corresponding radiating elements.
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公开(公告)号：US20240106105A1
公开(公告)日：2024-03-28
申请号：US18469605
申请日：2023-09-19
Applicant: NXP B.V.
Inventor： Waqas Hassan Syed , Ralph Matthijs van Schelven , Giorgio Carluccio , Pieter Lok , Antonius Johannes Matheus de Graauw , Konstantinos Doris , Daniele Cavallo , Andrea Neto
CPC classification number: H01Q1/2283 , H01Q1/42 , H01Q21/061
Abstract: In accordance with a first aspect of the present disclosure, an antenna unit is provided, comprising: an integrated circuit package containing an integrated circuit die and an antenna structure coupled to the integrated circuit die; a dielectric layer separated from the integrated circuit package, wherein the dielectric layer is placed at a predefined distance above an upper surface of the integrated circuit package. In accordance with a second aspect of the present disclosure, a corresponding method of producing an antenna unit is conceived.
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公开(公告)号：US11777204B2
公开(公告)日：2023-10-03
申请号：US17453199
申请日：2021-11-02
Applicant: NXP B.V.
Inventor： Giorgio Carluccio , Michael B. Vincent , Maristella Spella , Antonius Johannes Matheus de Graauw , Harshitha Thippur Shivamurthy
CPC classification number: H01Q1/46 , H01Q1/2283
Abstract: A package includes an integrated circuit, IC, die having circuitry configured to generate signalling for transmission to a waveguide and/or receive signalling from a waveguide via a launcher. The die is coupled to an interconnect layer extending out from a footprint of the die. The launcher is formed in a launcher-substrate, separate from the die. The launcher is coupled to the die to pass the signalling therebetween by a connection in the interconnect layer. The launcher includes a launcher element mounted in a first plane within the launcher-substrate and a waveguide-cavity including a ground plane arranged opposed to and spaced from the first plane. The waveguide-cavity is further defined by at least one side wall extending from the ground plane towards the first plane. The die and launcher are at least partially surrounded by mould material of the package.
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公开(公告)号：US11664567B2
公开(公告)日：2023-05-30
申请号：US17106269
申请日：2020-11-30
Applicant: NXP B.V.
Inventor： Adrianus Buijsman , Abdellatif Zanati , Giorgio Carluccio
CPC classification number: H01P3/12 , H01L23/66 , H01P3/121 , H01P5/107 , H01P11/002 , H01Q1/3233 , H01Q1/38 , H05K3/4697 , H01L2223/6627 , H05K2201/037 , H05K2201/09009
Abstract: A method of manufacturing a device is provided. The method includes forming a first cavity in a first substrate with the first cavity having a first depth. A second cavity is formed in a second substrate with the second cavity having a second depth. The first cavity and the second cavity are aligned with each other. The first substrate is affixed to the second substrate to form a waveguide substrate having a hollow waveguide with a first dimension substantially equal to the first depth plus the second depth. A conductive layer is formed on the sidewalls of the hollow waveguide. The waveguide substrate is placed over a packaged semiconductor device, the hollow waveguide aligned with a launcher of the packaged semiconductor device.
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公开(公告)号：US20220231408A1
公开(公告)日：2022-07-21
申请号：US17453199
申请日：2021-11-02
Applicant: NXP B.V.
Inventor： Giorgio Carluccio , Michael B. Vincent , Maristella Spella , Antonius Johannes Matheus de Graauw , Harshitha Thippur Shivamurthy
Abstract: A package comprising, an integrated circuit, IC, die comprising circuitry configured to generate signalling for transmission to a waveguide and/or receive signalling from a waveguide via a launcher, the die coupled to an interconnect layer extending out from a footprint of the die; and the launcher is formed in a launcher-substrate, separate from the die, the launcher coupled to the die to pass said signalling therebetween by a connection in said interconnect layer, wherein said launcher comprises a launcher element mounted in a first plane within the launcher-substrate and a waveguide-cavity comprising a ground plane arranged opposed to and spaced from the first plane, the waveguide-cavity further defined by at least one side wall extending from the ground plane towards the first plane; and wherein said die and said launcher are at least partially surrounded by mould material of said package.
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