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公开(公告)号：US09838197B2
公开(公告)日：2017-12-05
申请号：US15094618
申请日：2016-04-08
Applicant: NXP B.V.
Inventor： Juhui Li , Ghiath Al-kadi , Massimo Ciacci
IPC: H04L27/22 , H04L7/033 , H04L27/233 , H04L7/00
CPC classification number: H04L7/033 , H04L1/0079 , H04L7/0016 , H04L27/2331
Abstract: A system and module for, and a method of correcting, memory misalignment in a phase shift keying receiver is disclosed. Embodiments include a system having: an analog front end for receiving a demodulated signal having a preamble portion, and for generating a digital register input signal including a received preamble portion; a finite state machine for selecting a memory address of the demodulated signal based on the received preamble portion; a preamble memory for storing all possible preambles contained within the demodulated signal and for supplying a selected preamble memory output corresponding to the selected memory address; and a memory alignment module configured to compare phase information of symbols of the preamble portion and preamble phase information of symbols of the selected preamble memory output. This system checks that the preamble portion of the register input signal aligns with the selected preamble memory output and makes corrections when necessary.
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公开(公告)号：US20160301523A1
公开(公告)日：2016-10-13
申请号：US15094618
申请日：2016-04-08
Applicant: NXP B.V.
Inventor： Juhui Li , Ghiath Al-kadi , Massimo Ciacci
CPC classification number: H04L7/033 , H04L1/0079 , H04L7/0016 , H04L27/2331
Abstract: A system and module for, and a method of correcting, memory misalignment in a phase shift keying receiver is disclosed. Embodiments include a system having: an analog front end for receiving a demodulated signal having a preamble portion, and for generating a digital register input signal including a received preamble portion; a finite state machine for selecting a memory address of the demodulated signal based on the received preamble portion; a preamble memory for storing all possible preambles contained within the demodulated signal and for supplying a selected preamble memory output corresponding to the selected memory address; and a memory alignment module configured to compare phase information of symbols of the preamble portion and preamble phase information of symbols of the selected preamble memory output. This system checks that the preamble portion of the register input signal aligns with the selected preamble memory output and makes corrections when necessary.
Abstract translation: 公开了一种用于相移键控接收机中的存储器未对准的系统和模块，以及校正存储器未对准的方法。 实施例包括具有：模拟前端，用于接收具有前同步码部分的解调信号，并用于产生包括接收到的前导码部分的数字寄存器输入信号; 有限状态机，用于基于所接收的前同步码部分选择解调信号的存储器地址; 前导码存储器，用于存储包含在解调信号内的所有可能的前导码，并用于提供对应于所选存储器地址的所选择的前同步码存储器输出; 以及存储器对准模块，被配置为比较所述前导码部分的符号的相位信息和所选择的前导码存储器输出的符号的前导码相位信息。 该系统检查寄存器输入信号的前导码部分与所选择的前同步码存储器输出对齐，并在必要时进行校正。
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公开(公告)号：US20150318979A1
公开(公告)日：2015-11-05
申请号：US14702645
申请日：2015-05-01
Applicant: NXP B.V.
Inventor： Massimo Ciacci , Ghiath Al-kadi , Remco van de Beek
CPC classification number: H04L7/0276 , H04L7/0012 , H04L7/0332 , H04L7/0334
Abstract: A symbol clock recovery circuit comprising an ADC, a controllable inverter and a timing detector. A timing detector input terminal is configured to receive an ADC output signal from an ADC output terminal; a timing detector output terminal is configured to provide a digital output signal; and a first timing detector feedback terminal is configured to provide a first feedback signal to the inverter control terminal. The timing detector is configured to determine an error signal associated with the received ADC output signal, and set the first feedback signal in accordance with the error signal.
Abstract translation: 一种符号时钟恢复电路，包括ADC，可控逆变器和定时检测器。 定时检测器输入端子被配置为从ADC输出端子接收ADC输出信号; 定时检测器输出端被配置为提供数字输出信号; 并且第一定时检测器反馈端子被配置为向所述逆变器控制端子提供第一反馈信号。 定时检测器被配置为确定与接收的ADC输出信号相关联的误差信号，并且根据误差信号设置第一反馈信号。
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公开(公告)号：US20150172080A1
公开(公告)日：2015-06-18
申请号：US14133267
申请日：2013-12-18
Applicant: NXP B.V.
Inventor： Remco Cornelis Herman van de Beek , Massimo Ciacci , Ghiath Al-kadi
CPC classification number: H04L25/06 , G06K19/0715 , G06K19/07771 , H03F1/30 , H03F2200/375 , H04L27/06
Abstract: A proximity integrated circuit card bias adjustment. In one example, a decoding circuit, having an decoding range, for translating a data-frame signal having an information portion and a bias portion into an output code; and a bias adjust circuit coupled to receive the output code from the decoding circuit, and adjust the bias portion of the data-frame signal such that the output code is within the decoding range is disclosed. In another example, a method for proximity integrated circuit card bias adjustment, comprising: translating a data-frame signal having an information portion and a bias portion into an output code; and adjusting the bias portion of the data-frame signal such that the output code is within a decoding range is disclosed.
Abstract translation: 近程集成电路卡偏置调整。 在一个示例中，具有用于将具有信息部分和偏置部分的数据帧信号转换成输出代码的解码范围的解码电路; 以及偏置调整电路，其耦合以从解码电路接收输出代码，并且调整数据帧信号的偏置部分，使得输出代码处于解码范围内。 在另一示例中，一种用于近程集成电路卡偏移调整的方法，包括：将具有信息部分和偏置部分的数据帧信号转换为输出代码; 并且公开了数据帧信号的偏置部分，使得输出码在解码范围内。
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公开(公告)号：US08928401B2
公开(公告)日：2015-01-06
申请号：US13684886
申请日：2012-11-26
Applicant: NXP B.V.
Inventor： Jos Verlinden , Remco van de Beek , Massimo Ciacci
IPC: H03G1/04 , H03F3/68 , H03F3/217 , H03M1/66 , H03F3/00 , H03F3/21 , H03F3/24 , H03F3/189 , H03M1/80
CPC classification number: H03G1/04 , H03F3/005 , H03F3/189 , H03F3/211 , H03F3/2175 , H03F3/245 , H03F3/68 , H03M1/662 , H03M1/804
Abstract: Signals are processed to facilitate the mitigation and/or cancellation of undesirable components within the signal. As consistent with one or more embodiments, input/delay circuits offset the phase of an input signal, as presented to respective amplifiers. The phase offset is used, upon combination of the outputs of the respective amplifiers, to cancel the undesirable components of the signal. Such an approach may, for example, involve phase offset in a digital domain, with correction upon combination of the signals as presented in an analog domain.
Abstract translation: 对信号进行处理以便于消除和/或消除信号内不期望的组件。 与一个或多个实施例一致，输入/延迟电路将输入信号的相位偏移到相应的放大器。 在相应放大器的输出组合时，使用相位偏移来消除信号的不期望的分量。 例如，这种方法可以涉及在数字域中的相位偏移，并且在模拟域中呈现的信号的组合进行校正。
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Patent Agency Ranking
公开(公告)号：US20140192931A1
公开(公告)日：2014-07-10
申请号：US13736264
申请日：2013-01-08
Applicant: NXP B.V.
Inventor： Remco C. VandeBeek , Massimo Ciacci , Ghiath Al-kadi
IPC: H04L27/06
CPC classification number: H04L27/06 , H04B5/0031 , H04B5/0075
Abstract: In one embodiment, an apparatus is provided that includes a first circuit configured and arranged to provide a modulated carrier signal in response to a signal provided from the antenna. The modulated carrier signal conveys data using peaks or amplitudes of the carrier signal. A second circuit is configured to rectify the modulated carrier signal and integrate the rectified signal in response to a first clock signal. A third circuit is coupled to an output of the second circuit and is configured to sample the integrated signal values and provide therefrom a sample-based approximation of the modulated carrier signal.
Abstract translation: 在一个实施例中，提供一种装置，其包括配置和布置为响应于从天线提供的信号来提供调制载波信号的第一电路。 调制的载波信号使用载波信号的峰值或幅度来传送数据。 第二电路被配置为对已调制载波信号进行整流，并响应于第一时钟信号对经整流的信号进行积分。 第三电路耦合到第二电路的输出，并且被配置为对积分信号值进行采样，并从其提供调制载波信号的基于样本的近似。
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公开(公告)号：US10812119B1
公开(公告)日：2020-10-20
申请号：US16445924
申请日：2019-06-19
Applicant: NXP B.V.
Abstract: Interference cancellation is provided, according to certain aspects, by a filter, a signal detection circuit, synthesis circuitry and signal-generation circuitry. The filter is used to filter an incoming signal having an associated signal-to-noise metric and to output therefrom a filtered signal having an interference attribute of the incoming signal by amplification and/or isolation. The signal detection circuit is used to detect the interference attribute in the filtered signal. The synthesis circuitry is used to synthesize interference in the incoming signal based on the interference attribute. The signal-generation circuitry is used to generate, in response to the synthesized interference in the incoming signal, a filtered version of the incoming signal which provides an improved signal-to-noise metric.
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公开(公告)号：US20170078085A1
公开(公告)日：2017-03-16
申请号：US15267099
申请日：2016-09-15
Applicant: NXP B.V.
Inventor： Adaickalavan Meiyappan , Juhui Li , Ghiath Al-Kadi , Massimo Ciacci
CPC classification number: H04L7/06 , H04L25/03006 , H04L25/06 , H04L25/066 , H04L25/4923 , H04L27/06 , H04L43/087
Abstract: A differential detector for a receiver and a method of detecting the value of symbols of a signal is disclosed. In particular, a detector comprising: an analog to digital converter (110) for sampling samples (232) from symbols (234) of a signal (230); a differentiator (130) configured to differentiate the samples with a transfer function to produce a differentiated series of samples for each symbol; and a decision device configured to determine the value of each symbol by comparing values of the differentiated series of samples with boundary condition values.
Abstract translation: 公开了一种用于接收机的差分检测器和检测信号符号值的方法。 特别地，一种检测器，包括：模数转换器（110），用于从信号（230）的符号（234）中采样采样（232）; 一个微分器（130），被配置成用传递函数来区分样本以产生每个符号的差分系列样本; 以及判定装置，被配置为通过将所述差分的一系列样本的值与边界条件值进行比较来确定每个符号的值。
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公开(公告)号：US20150254543A1
公开(公告)日：2015-09-10
申请号：US14719781
申请日：2015-05-22
Applicant: NXP B.V.
Inventor： Ghiath Al-Kadi , Massimo Ciacci , Remco Cornelis Herman van de Beek
CPC classification number: G06K19/0723 , G06K19/07 , H04L1/0053 , H04L1/0075 , H04L1/20 , H04W4/80 , Y02D70/166
Abstract: The invention proposes a smart card which comprises a digital signal processing receiver that can automatically identify the type of a smart card reader based on the error vector magnitude of signals received from the reader. The digital signal processing receiver is able to reconfigure itself at runtime in order to optimally minimize its power consumption in dependence on the type of reader it is communicating with. Furthermore, the invention proposes a new preamble structure that comprises a basic part and an optional additional part.
Abstract translation: 本发明提出了一种智能卡，其包括数字信号处理接收器，其可以基于从读取器接收的信号的误差向量大小自动识别智能卡读卡器的类型。 数字信号处理接收器能够在运行时重新配置自身，以便根据其正在通信的读取器的类型来最佳化其功耗。 此外，本发明提出了一种新的前导码结构，其包括基本部分和可选的附加部分。
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公开(公告)号：US08842720B2
公开(公告)日：2014-09-23
申请号：US13929670
申请日：2013-06-27
Applicant: NXP B.V.
Inventor： Remco Cornelis Herman van de Beek , Massimo Ciacci , Jos Verlinden , Ghaith Al-kadi
CPC classification number: H04L25/03891 , H03F1/3241 , H03F3/195 , H03F3/24 , H04L25/03343 , H04L25/49 , H04L27/368
Abstract: The method comprises receiving an input stream of symbols (x(i)) representing a phase change and magnitude of an RF signal, the magnitudes of the symbols are constant, the phase changes of the symbols encode digital information, and adjust the input stream of symbols to reduce inter-symbol interference. The adjusting iteratively determines a next symbol of the equalized stream (x′(n)) after receiving a next symbol of the input stream (x(n)) by multiplying the next symbol of the input stream (x(n)) with a next adjusting real number (a(n)), multiplying a previous symbol of the input stream (x(n−1)) with a previous adjusting real number (a(n−1)), the previous symbol being received before the next symbol of the input stream, and the next symbol of the equalized stream is computed from the multiplied next symbol and the multiplied previous symbol of the input stream.
Abstract translation: 该方法包括接收表示RF信号的相位变化和幅度的符号（x（i））的输入流，符号的大小是恒定的，符号的相位变化对数字信息进行编码，并且调整输入流 符号以减少符号间干扰。 在通过将输入流（x（n））的下一个符号乘以输入流（x（n））的下一个符号之后，通过将输入流（x（n））的下一个符号与 下一个调整实数（a（n）），将输入流的先前符号（x（n-1））与先前的调整实数（a（n-1））相乘），先前的符号在下一个 输入流的符号，并且均衡流的下一个符号从乘法的下一个符号和输入流的相乘的先前符号计算。
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