公开(公告)号：AU2003201066A8

公开(公告)日：2003-07-30

申请号：AU2003201066

申请日：2003-01-14

Applicant: PHILIPS INTELLECTUAL PROPERTY

Inventor： HAPKE FRIEDRICH

IPC: G01R31/28 ,  G01R31/3181 ,  G01R31/3183 ,  G01R31/3185 ,  G01R31/3187

Abstract: An integrated circuit ( 14 ) with an application circuit ( 1 ) to be tested and a self-testing circuit ( 5 - 13 ), which is provided for testing the application circuit ( 1 ) and generates pseudorandom test patterns, which can be transformed, by means of first logic gates ( 6, 7, 8 ) and signals externally fed to said gates, into deterministic test vectors, which are fed to the application circuit ( 1 ) for testing purposes, wherein the output signals occurring through the application circuit ( 1 ) as a function of the test patterns are evaluated by means of a signature register ( 13 ), wherein, by means of second logic gates ( 10, 11, 12 ) and signals fed to said gates, those bits of the output signals of the application circuit ( 1 ) which, due to the circuit structure of application circuit ( 1 ), have undefined states, are blocked during testing.

公开(公告)号：DE50204985D1

公开(公告)日：2005-12-29

申请号：DE50204985

申请日：2002-03-05

Applicant: PHILIPS INTELLECTUAL PROPERTY

Inventor： HAPKE FRIEDRICH

IPC: G01R31/3183 ,  G01R31/3181 ,  G01R31/319 ,  G01R31/3193 ,  G06F11/22

公开(公告)号：DE50105516D1

公开(公告)日：2005-04-14

申请号：DE50105516

申请日：2001-08-07

Applicant: PHILIPS INTELLECTUAL PROPERTY

Inventor： HAPKE FRIEDRICH ,  SOLBACH RUEDIGER ,  GLOWATZ ANDREAS

IPC: G01R31/28 ,  G01R31/317 ,  G01R31/3183 ,  G01R31/3185

公开(公告)号：DE50105446D1

公开(公告)日：2005-04-07

申请号：DE50105446

申请日：2001-08-08

Applicant: PHILIPS INTELLECTUAL PROPERTY

Inventor： HAPKE FRIEDRICH

IPC: G01R31/28 ,  G01R31/3183 ,  G01R31/3185 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04

Abstract: Arrangement for testing an integrated circuit with a combinational logic circuit. The combination logic unit is tested by comparison of its behavior with test software that emulates the theoretical behavior of the circuit. The test software comprises two identical software modules (11, 16) for the combinational logic circuit, with a test pattern applied to the first module and its output signals connected to the second module.

公开(公告)号：AU2003201066A1

公开(公告)日：2003-07-30

申请号：AU2003201066

申请日：2003-01-14

Applicant: PHILIPS INTELLECTUAL PROPERTY

Inventor： HAPKE FRIEDRICH

IPC: G01R31/28 ,  G01R31/3181 ,  G01R31/3183 ,  G01R31/3185 ,  G01R31/3187

Abstract: An integrated circuit ( 14 ) with an application circuit ( 1 ) to be tested and a self-testing circuit ( 5 - 13 ), which is provided for testing the application circuit ( 1 ) and generates pseudorandom test patterns, which can be transformed, by means of first logic gates ( 6, 7, 8 ) and signals externally fed to said gates, into deterministic test vectors, which are fed to the application circuit ( 1 ) for testing purposes, wherein the output signals occurring through the application circuit ( 1 ) as a function of the test patterns are evaluated by means of a signature register ( 13 ), wherein, by means of second logic gates ( 10, 11, 12 ) and signals fed to said gates, those bits of the output signals of the application circuit ( 1 ) which, due to the circuit structure of application circuit ( 1 ), have undefined states, are blocked during testing.

公开(公告)号：DE50107889D1

公开(公告)日：2005-12-08

申请号：DE50107889

申请日：2001-08-02

Applicant: PHILIPS INTELLECTUAL PROPERTY

Inventor： HAPKE FRIEDRICH

IPC: G01R31/28 ,  G01R31/3181 ,  G01R31/3185 ,  G06F11/22 ,  G01R31/3187

Abstract: Integrated circuit has application circuit (1) and self-test circuit (5-16). Device (5-9) generates a deterministic test pattern that is applied to the application circuit, the output from which is evaluated using a signature register. The self-test circuit provides masking logic (14) that blocks output bits of application circuit that would be undefined during testing, so only the remaining defined bits are passed to the signature register (13).

公开(公告)号：DE10209078A1

公开(公告)日：2003-09-18

申请号：DE10209078

申请日：2002-03-01

Applicant: PHILIPS INTELLECTUAL PROPERTY

Inventor： HAPKE FRIEDRICH

IPC: G01R31/28 ,  G01R31/3181 ,  G01R31/3183 ,  G01R31/3185 ,  H01L21/822 ,  H01L27/04 ,  G01R31/3187

Abstract: Integrated circuit with an application circuit ( 1 ) to be tested, and a self-test circuit ( 5 - 16 ) which is provided for testing the application circuit ( 1 ) and comprises an arrangement ( 5 - 9 ) for generating desired test patterns which are applied to the application circuit ( 1 ) for test purposes, wherein the output signals occurring in dependence upon the test patterns through the application circuit ( 1 ) are evaluated by means of a signature register ( 13 ), the arrangement ( 5 - 9 ) for generating the desired test patterns comprising a bit modification circuit ( 9 ) which individually controls first control inputs of combination logics ( 6, 7, 8 ) in such a way that a pseudo-random sequence of test patterns supplied by a shift register is modified such that, by approximation, the desired test patterns are obtained, and which controls second control inputs of the combination logics ( 6, 7, 8 ), by means of which the first control inputs can be blocked, such that those test patterns that are supplied by the shift register ( 5 ) and are already desired test patterns are not modified by the bit modification circuit ( 9 ) by means of controlling the first control inputs of the combination logics ( 6, 7, 8 ).

公开(公告)号：DE10201554A1

公开(公告)日：2003-08-21

申请号：DE10201554

申请日：2002-01-17

Applicant: PHILIPS INTELLECTUAL PROPERTY

Inventor： HAPKE FRIEDRICH

IPC: G01R31/28 ,  G01R31/3181 ,  G01R31/3183 ,  G01R31/3185 ,  G01R31/3187

Abstract: An integrated circuit ( 14 ) with an application circuit ( 1 ) to be tested and a self-testing circuit ( 5 - 13 ), which is provided for testing the application circuit ( 1 ) and generates pseudorandom test patterns, which can be transformed, by means of first logic gates ( 6, 7, 8 ) and signals externally fed to said gates, into deterministic test vectors, which are fed to the application circuit ( 1 ) for testing purposes, wherein the output signals occurring through the application circuit ( 1 ) as a function of the test patterns are evaluated by means of a signature register ( 13 ), wherein, by means of second logic gates ( 10, 11, 12 ) and signals fed to said gates, those bits of the output signals of the application circuit ( 1 ) which, due to the circuit structure of application circuit ( 1 ), have undefined states, are blocked during testing.

公开(公告)号：AU2003206075A1

公开(公告)日：2003-09-16

申请号：AU2003206075

申请日：2003-02-26

Applicant: PHILIPS INTELLECTUAL PROPERTY

Inventor： HAPKE FRIEDRICH

IPC: G01R31/28 ,  G01R31/3181 ,  G01R31/3183 ,  G01R31/3185 ,  H01L21/822 ,  H01L27/04 ,  G01R31/3187

Abstract: Integrated circuit with an application circuit ( 1 ) to be tested, and a self-test circuit ( 5 - 16 ) which is provided for testing the application circuit ( 1 ) and comprises an arrangement ( 5 - 9 ) for generating desired test patterns which are applied to the application circuit ( 1 ) for test purposes, wherein the output signals occurring in dependence upon the test patterns through the application circuit ( 1 ) are evaluated by means of a signature register ( 13 ), the arrangement ( 5 - 9 ) for generating the desired test patterns comprising a bit modification circuit ( 9 ) which individually controls first control inputs of combination logics ( 6, 7, 8 ) in such a way that a pseudo-random sequence of test patterns supplied by a shift register is modified such that, by approximation, the desired test patterns are obtained, and which controls second control inputs of the combination logics ( 6, 7, 8 ), by means of which the first control inputs can be blocked, such that those test patterns that are supplied by the shift register ( 5 ) and are already desired test patterns are not modified by the bit modification circuit ( 9 ) by means of controlling the first control inputs of the combination logics ( 6, 7, 8 ).

公开(公告)号：WO2006003596A3

公开(公告)日：2006-05-11

申请号：PCT/IB2005052115

申请日：2005-06-27

Applicant: PHILIPS INTELLECTUAL PROPERTY ,  KONINKL PHILIPS ELECTRONICS NV ,  WITTKE MICHAEL ,  HAPKE FRIEDRICH

Inventor： WITTKE MICHAEL ,  HAPKE FRIEDRICH

IPC: G01R31/3187

CPC classification number: G01R31/3187

Abstract: The object being to develop an integrated circuit arrangement (100) with at least one application circuit (40) to be tested, and with at least one self-test circuit (10, 20, 32, 34, 36, 50) provided for testing the application circuit (40) and generating at least one pseudo-random test sample, wherein said pseudo-random test sample can be converted into at least one test vector that is programmable and/or deterministic and that can be supplied to the application circuit (40) for testing purposes via at least one logic gate (32, 34, 36) and by means of at least one signal that can be applied to said logic gate (32, 34, 36), and wherein the output signal arising in dependence on the deterministic test vector can be evaluated by the application circuit (40) by means of at least one signature register (50), as well as a method of testing the application circuit (40) present in the integrated circuit arrangement (100) by means of the self-test circuit (10, 20, 32, 34, 36, 50) further such that the B[uild-]I[n]S[elf-]T[est] hardware connected to the additional deterministic logic can be reduced, it is suggested that the signal to be supplied to the logic gate (32, 34, 36) can be made available by a B[it]F[lipping]F[unction] logic circuit (10) based on at least one

Abstract translation: 目的是开发具有待测试的至少一个应用电路（40）的集成电路装置（100），以及提供用于测试的至少一个自测电路（10,20,32,34,36,50） 所述应用电路（40）并且生成至少一个伪随机测试样本，其中所述伪随机测试样本可以被转换成至少一个可编程和/或确定性的测试向量，并且可被提供给应用电路 40）用于通过至少一个逻辑门（32,34,36）进行测试，并且借助于可以施加到所述逻辑门（32,34,36）的至少一个信号，并且其中依赖于所述输出信号 可以通过至少一个签名寄存器（50）由应用电路（40）对确定性测试向量进行评估，以及通过以下方式测试集成电路装置（100）中存在的应用电路（40）的方法： 自检电路的装置（10,20,32,34,36,50）进一步如此 可以减少连接到附加确定性逻辑的B [uild-] I [n] S [elf-] T [est]硬件，建议提供给逻辑门（32,34,36）的信号 ）可以由B [it] F [lipping] F [unction]逻辑电路（10）基于至少一个