公开(公告)号：JP2001168698A

公开(公告)日：2001-06-22

申请号：JP2000327139

申请日：2000-10-26

Applicant: PIXTECH SA

Inventor： BANCAL BERNARD ,  PEYRON PHILIPPE

IPC: H03K17/10 ,  H03K17/687

Abstract: PROBLEM TO BE SOLVED: To provide a push-pull type switch where all the transistors are the same type. SOLUTION: The push-pull switch has a first N-channel MOS transistor where a drain-source path is connected between a high voltage terminal and an output terminal, a first resistor to be connected between the gate of a first transistor and the high voltage terminal, a diode having an anode to be connected to the output terminal and a cathode to be connected to the gate of the first transistor, a second N-channel MOS transistor having a drain to be connected to the cathode of the diode, a source to be connected to a reference potential and a gate to be connected to a control terminal, and a second resister to be connected between the gate of a second transistor and the output terminal.

公开(公告)号：JPH11191358A

公开(公告)日：1999-07-13

申请号：JP28866698

申请日：1998-09-28

Applicant: PIXTECH SA

Inventor： BANCAL BERNARD ,  PEYRE JEAN-FRANCOIS ,  PEYRON PHILIPPE

IPC: H01J29/04 ,  G09G3/22 ,  H01J1/304 ,  H01J31/12 ,  H01J1/30

Abstract: PROBLEM TO BE SOLVED: To simplify the structure of an amplifier to be addressed by providing a grid suitable to be successively addressed and connecting a return electrode suitable to independently and simultaneously address thereto through a resistance element. SOLUTION: Each control amplifier 21 is connected between grid lines 14 corresponding to a high address voltage +Vg so as to be independently and successively addressable. Each transistor P is controlled by a 2-state signal C, and the grid line 14 is addressed when the signal C is in a potential sufficiently lower than the potential +Vg for ON of the corresponding transistor P. Therefore, the not-addressed grid line 14 is left as it is in a floating potential seen from the control amplifier 21. Each grid line 14 is connected to an extremely thin conductor 23 biased to a low potential -Vg through a resistance area 22, so that each grid liner 14 is returned to the potential sufficiently low to prevent the electron emission by the grid line 14 at the end of address by this resistance area 22.

公开(公告)号：FR2800532B1

公开(公告)日：2002-01-04

申请号：FR9913752

申请日：1999-10-28

Applicant: PIXTECH SA

Inventor： BANCAL BERNARD ,  PEYRON PHILIPPE

IPC: H03K17/10 ,  H03K17/687

公开(公告)号：FR2769114A1

公开(公告)日：1999-04-02

申请号：FR9712392

申请日：1997-09-30

Applicant: PIXTECH SA

Inventor： BANCAL BERNARD ,  PEYRE JEAN FRANCOIS ,  PEYRON PHILIPPE

IPC: H01J29/04 ,  G09G3/22 ,  H01J1/304 ,  H01J31/12 ,  G09G3/20

Abstract: The display screen has a micro-point cathode emitting electrons and an associated grid to extract the electrons. The cathode/grid is formed from conductive rows (15') which can be addressed sequentially and perpendicular columns (14') that can be addressed individually and simultaneously during addressing of the rows. A return electrode (30) set to a positive potential is connected via a resistance to each grid or cathode row.

公开(公告)号：FR2800532A1

公开(公告)日：2001-05-04

申请号：FR9913752

申请日：1999-10-28

Applicant: PIXTECH SA

Inventor： BANCAL BERNARD ,  PEYRON PHILIPPE

IPC: H03K17/10 ,  H03K17/687

公开(公告)号：FR2769114B1

公开(公告)日：1999-12-17

申请号：FR9712392

申请日：1997-09-30

Applicant: PIXTECH SA

Inventor： BANCAL BERNARD ,  PEYRE JEAN FRANCOIS ,  PEYRON PHILIPPE

IPC: H01J29/04 ,  G09G3/22 ,  H01J1/304 ,  H01J31/12 ,  G09G3/20

Abstract: The display screen has a micro-point cathode emitting electrons and an associated grid to extract the electrons. The cathode/grid is formed from conductive rows (15') which can be addressed sequentially and perpendicular columns (14') that can be addressed individually and simultaneously during addressing of the rows. A return electrode (30) set to a positive potential is connected via a resistance to each grid or cathode row.