公开(公告)号：US20230370083A1

公开(公告)日：2023-11-16

申请号：US18022071

申请日：2021-06-15

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Koji OBATA

IPC: H03M1/46

CPC classification number: H03M1/46

Abstract: A comparator compares a differential voltage between a voltage to be converted as an analog input voltage and a comparative voltage generated by a D/A converting unit with a comparison reference voltage. A switching circuit selectively connects a capacitor, associated with the analog input voltage selected as the voltage to be converted, to an output terminal of an integrator. The integrator integrates the differential voltage in a state where an A/D converting section has performed conversion operation on a least significant bit. A comparison reference voltage generating unit uses, as the comparison reference voltage, a charge voltage for the capacitor associated with the analog input voltage selected as the voltage to be converted.

公开(公告)号：US20230197711A1

公开(公告)日：2023-06-22

申请号：US17995972

申请日：2021-04-14

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Shoichi GOTO ,  Koji OBATA ,  Masaru SASAGO ,  Masamichi NAKAGAWA

IPC: H01L27/06 ,  H01L25/065 ,  G11C5/02 ,  H01L27/02 ,  G06N3/065

CPC classification number: H01L27/0688 ,  H01L25/0657 ,  G11C5/02 ,  H01L27/0207 ,  G06N3/065

Abstract: An artificial intelligence (AI) chip includes: a plurality of memory dies each for storing data; a plurality of computing dies each of which performs a computation included in an AI process; and a system chip that controls the plurality of memory dies and the plurality of computing dies. Each of the plurality of memory dies has a first layout pattern. Each of the plurality of computing dies has a second layout pattern. A second memory die which is one of the plurality of memory dies is stacked above the first layout pattern of a first memory die which is one of the plurality of memory dies. A second computing die which is one of the plurality of computing dies is stacked above the second layout pattern of a first computing die which is one of the plurality of computing dies.

公开(公告)号：US20230122673A1

公开(公告)日：2023-04-20

申请号：US17911614

申请日：2021-03-09

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Junko ONOZAKI ,  Koji OBATA ,  Hisashi AIKAWA ,  Yuya SUGASAWA

IPC: G06N20/00

Abstract: A data generation method includes a first acquisition step, a second acquisition step, and a generation step. The first acquisition step includes acquiring result information about a result of a classification executed by a living being on a target. The second acquisition step includes acquiring execution information about execution of the classification. The generation step includes generating data for machine learning based on the result information and the execution information. The data for machine learning includes learning data and evaluation information about evaluation of the learning data.

公开(公告)号：US20240038726A1

公开(公告)日：2024-02-01

申请号：US18264194

申请日：2021-12-21

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Koji OBATA ,  Masaru SASAGO ,  Masamichi NAKAGAWA ,  Tatsuya KABE ,  Hiroyuki GOMYO ,  Masatomo MITSUHASHI ,  Yutaka SONODA

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/00 ,  H01L27/02 ,  H10B80/00

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/16 ,  H01L27/0207 ,  H01L24/08 ,  H10B80/00 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06544 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2224/16146 ,  H01L2224/48225 ,  H01L2224/32225 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/08145

Abstract: An AI module includes a first semiconductor chip. The first semiconductor chip includes a plurality of operation blocks each of which performs a predetermined operation and a plurality of memory blocks each including memory. The plurality of operation blocks and the plurality of memory blocks are arranged in a checkered pattern or in a striped pattern in plan view.

公开(公告)号：US20230344442A1

公开(公告)日：2023-10-26

申请号：US18245815

申请日：2021-06-10

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Jun'ichi NAKA ,  Koji OBATA

IPC: H03M1/46

CPC classification number: H03M1/46 ,  G01P1/00

Abstract: A D/A converting unit generates a comparative voltage corresponding to a target bit falling within a range from a most significant bit through a least significant bit. A comparator determines a value of the target bit by comparing a differential voltage between an output signal of an input switching unit and a comparative voltage generated by the D/A converting unit with a reference voltage. An integrator integrates a conversion error. In a first conversion operation of converting a first signal, a control unit sets, based on a result obtained by the integrator, the reference voltage for use when the first signal to be provided next time as the output signal by the input switching unit is A/D converted. In a second conversion operation of A/D converting a second signal, the control unit sets the reference voltage at a constant voltage level.

公开(公告)号：US20220173746A1

公开(公告)日：2022-06-02

申请号：US17442088

申请日：2020-02-28

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Junji NAKATSUKA ,  Hiroki YOSHINO ,  Jun'ichi NAKA ,  Koji OBATA ,  Masaaki NAGAI

IPC: H03M1/14 ,  H03M1/38 ,  H03M3/00

Abstract: An A/D converter includes an A/D conversion unit and an output unit. The A/D conversion unit includes a second A/D converter (successive approximation register A/D converter) and generates first digital data having a first number of bits and second digital data having a second number of bits, where the second number of bits is smaller than the first number of bits. The output unit provides first output information that is the first digital data and also provides second output information based on the second digital data. The output unit provides the second output information before providing the first output information.

公开(公告)号：US20220158652A1

公开(公告)日：2022-05-19

申请号：US17442303

申请日：2020-02-28

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Masaaki NAGAI ,  Hiroki YOSHINO ,  Junji NAKATSUKA ,  Jun'ichi NAKA ,  Koji OBATA

IPC: H03M3/00

Abstract: A digital filter is used in an A/D converter and includes a first filter and second filter. The first filter outputs first digital data by performing filter processing on output of an A/D conversion unit included in the A/D converter. The second filter outputs second digital data by performing filter processing on the output of the A/D conversion unit. The second digital data has either a lower resolution or a smaller effective number of bits than the first digital data does. The second filter outputs the second digital data before the first filter outputs the first digital data.