公开(公告)号：AU2003285122A1

公开(公告)日：2004-05-25

申请号：AU2003285122

申请日：2003-10-31

Applicant: QUALCOMM INC

Inventor： MALDONADO DAVID ,  DHALIWAL UPKAR ,  SHIU DA-SHAN ,  ZHANG LI ,  SY EUGENE

IPC: H03G3/30 ,  H04B1/38

Abstract: Techniques for improved low latency frequency switching are disclosed. In one embodiment, a controller receives a frequency switch command and generates a frequency switch signal at a time determined in accordance with a system timer. In another embodiment, gain calibration is initiated subsequent to the frequency switch signal delayed by the expected frequency synthesizer settling time. In yet another embodiment, DC cancellation control and gain control are iterated to perform gain calibration, with signaling to control the iterations without need for processor intervention. Various other embodiments are also presented. Aspects of the embodiments disclosed may yield the benefit of reducing latency during frequency switching, allowing for increased measurements at alternate frequencies, reduced time spent on alternate frequencies, and the capacity and throughput improvements that follow from minimization of disruption of an active communication session and improved neighbor selection.

公开(公告)号：BR0315822A

公开(公告)日：2005-09-13

申请号：BR0315822

申请日：2003-10-31

Applicant: QUALCOMM INC

Inventor： SHIU DA-SHAN ,  ZHANG LI ,  SY EUGENE ,  MALDONADO DAVID ,  DHALIWAL UPKAR

IPC: H03G3/30 ,  H04B1/40 ,  H04B1/30 ,  H03D3/00

Abstract: Techniques for improved low latency frequency switching are disclosed. In one embodiment, a controller receives a frequency switch command and generates a frequency switch signal at a time determined in accordance with a system timer. In another embodiment, gain calibration is initiated subsequent to the frequency switch signal delayed by the expected frequency synthesizer settling time. In yet another embodiment, DC cancellation control and gain control are iterated to perform gain calibration, with signaling to control the iterations without need for processor intervention. Various other embodiments are also presented. Aspects of the embodiments disclosed may yield the benefit of reducing latency during frequency switching, allowing for increased measurements at alternate frequencies, reduced time spent on alternate frequencies, and the capacity and throughput improvements that follow from minimization of disruption of an active communication session and improved neighbor selection.

公开(公告)号：AU2003285122A8

公开(公告)日：2004-05-25

申请号：AU2003285122

申请日：2003-10-31

Applicant: QUALCOMM INC

Inventor： MALDONADO DAVID ,  SHIU DA-SHAN ,  DHALIWAL UPKAR ,  SY EUGENE ,  ZHANG LI

IPC: H03G3/30 ,  H04B1/40 ,  H03D3/00 ,  H04B1/30

Abstract: Techniques for improved low latency frequency switching are disclosed. In one embodiment, a controller receives a frequency switch command and generates a frequency switch signal at a time determined in accordance with a system timer. In another embodiment, gain calibration is initiated subsequent to the frequency switch signal delayed by the expected frequency synthesizer settling time. In yet another embodiment, DC cancellation control and gain control are iterated to perform gain calibration, with signaling to control the iterations without need for processor intervention. Various other embodiments are also presented. Aspects of the embodiments disclosed may yield the benefit of reducing latency during frequency switching, allowing for increased measurements at alternate frequencies, reduced time spent on alternate frequencies, and the capacity and throughput improvements that follow from minimization of disruption of an active communication session and improved neighbor selection.

公开(公告)号：WO2004040787A2

公开(公告)日：2004-05-13

申请号：PCT/US0334784

申请日：2003-10-31

Applicant: QUALCOMM INC

Inventor： SHIU DA-SHAN ,  ZHANG LI ,  SY EUGENE ,  MALDONADO DAVID ,  DHALIWAL UPKAR

IPC: H03G3/30 ,  H04B1/38

CPC classification number: H03G3/3036

Abstract: Techniques for improved low latency frequency switching are disclosed. In one embodiment, a controller (510) receives a frequency switch command and generates a frequency switch signal at a time determined in accordance with a system timer (520). In another embodiment, gain calibration is initiated subsequent to the frequency switch signal delayed by the expected frequency synthesizer settling time. In yet another embodiment, DC cancellation control (540) and gain control (530) are iterated to perform gain calibration, with signaling to control the iterations without need for processor (550) intervention. Various other embodiments are also presented. Aspects of the embodiments disclosed may yield the benefit of reducing latency during frequency switching, allowing for increased measurements at alternate frequencies, reduced time spent on alternate frequencies, and the capacity and throughput improvements that follow from minimization of disruption of an active communication session and improved neighbor selection.

Abstract translation: 公开了用于改进的低延迟频率切换的技术。 在一个实施例中，控制器（510）接收频率切换命令并在根据系统定时器（520）确定的时间产生频率切换信号。 在另一个实施例中，在频率切换信号延迟预期的频率合成器建立时间之后，开始增益校准。 在又一个实施例中，迭代DC消除控制（540）和增益控制（530）以执行增益校准，利用信令来控制迭代而不需要处理器（550）干预。 还呈现了各种其他实施例。 所公开的实施例的各方面可以产生减少频率切换期间的等待时间的益处，允许在交替频率处增加测量，减少在替代频率上花费的时间，以及从最小化活动通信会话的中断之后改进容量和吞吐量，并且改进 邻居选择。