公开(公告)号：AU2017340249A1

公开(公告)日：2019-03-14

申请号：AU2017340249

申请日：2017-09-05

Applicant: QUALCOMM INC

Inventor： GARG MANISH

IPC: G11C7/10 ,  G11C8/08 ,  G11C8/10 ,  G11C11/418 ,  G11C11/419

Abstract: Memory systems that provide separate read and write address decoding to support simultaneous memory read and write operations are disclosed. Separating read and write address decoding can avoid circuit conflicts for a simultaneous memory read and write operation even if employing single port memory bit cells. The read and write addresses of respective read and write operations are separately decoded into read and write row and column selects driven to a memory array so that simultaneous read and write operations are not affected by each other. To avoid a circuit conflict for a simultaneous read and write operation, the memory system is configured to prioritize a write row select over a read row select to drive a row of memory bit cells in the memory array. In this manner, that write operation will always be successful regardless of whether the read and write row select are to the same row.

公开(公告)号：SG11202005643YA

公开(公告)日：2020-07-29

申请号：SG11202005643Y

申请日：2018-10-25

Applicant: QUALCOMM INC

Inventor： SHANKAR HARISH ,  GARG MANISH ,  NADKARNI RAHUL KRISHNAKUMAR ,  KUMAR RAJESH ,  PHAN MICHAEL

IPC: G11C7/08 ,  G11C7/10 ,  G11C11/419

Abstract: A memory system includes a sense amplifier electrically coupled to a first bitline and a second bitline associated with a column of a memory array, a bl transistor electrically coupled to the first bitline, wherein the bl transistor is configured to receive as input a first electrical signal from the first bitline, and a blb transistor electrically coupled to the second bitline, wherein the blb transistor is configured to receive as input a second electrical signal from the second bitline, wherein an output of the bl transistor and an output of the blb transistor are electrically coupled together as a common output, and wherein the sense amplifier is configured to receive as an input the common output of the bl transistor and the blb transistor.

公开(公告)号：IN4993CHN2014A

公开(公告)日：2015-09-18

申请号：IN4993CHN2014

申请日：2014-07-01

Applicant: QUALCOMM INC

Inventor： PUCKETT JOSHUA L ,  GARG MANISH ,  SHANKAR HARISH

IPC: G11C11/412 ,  G11C11/419

Abstract: In low power CPUs the best way to reduce power is to reduce supply voltage. Most low voltage memory arrays use an 8T cell (450) which has read stability immunity in order to operate at low voltages. An embodiment of the disclosure determines when a write wordline (WWL 410) rises. If the determination (header pFET 430) shows that the WWL has risen at least one of the plurality of p channel field effect transistors (pFETS 432 434) is disconnected from a voltage supply and the at least one plurality of n channel field effect transistors (nFET) pass gate transistors (440 442) are opened.

公开(公告)号：DE602007009365D1

公开(公告)日：2010-11-04

申请号：DE602007009365

申请日：2007-03-01

Applicant: QUALCOMM INC

Inventor： GARG MANISH ,  HAMDAN FADI ADEL

IPC: G01R31/3185 ,  G11C29/00 ,  H03K3/037

公开(公告)号：ES2847228T3

公开(公告)日：2021-08-02

申请号：ES17768324

申请日：2017-09-05

Applicant: QUALCOMM INC

Inventor： GARG MANISH

IPC: G11C7/10 ,  G11C8/08 ,  G11C8/10 ,  G11C11/418 ,  G11C11/419

Abstract: Un circuito de selección de células de bits de memoria (502) para un sistema de memoria que comprende células de bits de memoria de un solo puerto y configurado para decodificar por separado las direcciones de lectura y escritura de memoria en selecciones de fila y columna de lectura y escritura, respectivamente, el circuito de selección de células de bits de memoria configurado para: en respuesta a una operación de escritura en memoria: recibir una selección de fila de escritura (432) que indica una fila de células de bits de memoria (R(0)- R(N)) entre una pluralidad de filas de células de bits de memoria en una matriz de memoria correspondiente a una dirección de escritura en memoria para la operación de escritura en memoria; recibir una selección de columna de escritura (434) que indica una columna de células de bits de memoria (C(0)-C(M)) entre una pluralidad de columnas de células de bits de memoria en la matriz de memoria correspondiente a la dirección de escritura en memoria para la operación de escritura en memoria; seleccionar la columna de células de bits de memoria de las células de bits de memoria en la matriz de memoria direccionada por la selección de columna de escritura (434); y generar una selección de fila de lectura/escritura (526) que indica la operación de escritura en memoria; y seleccionar la fila de células de bits de memoria de células de bits de memoria en la matriz de memoria direccionada por la selección de fila de escritura (432) en respuesta a la selección de fila de lectura/escritura que indica la operación de escritura en memoria; y en respuesta a una operación de lectura de memoria: recibir una selección de fila de lectura (426) que indica una fila de células de bits de memoria (R(0)- R(N)) entre la pluralidad de filas de células de bits de memoria en la matriz de memoria correspondiente a una dirección de lectura de memoria para la operación de lectura de memoria; recibir una selección de columna de lectura (428) que indica una columna de células de bits de memoria (C(0)-C(M)) entre la pluralidad de columnas de células de bits de memoria en la matriz de memoria correspondiente a la dirección de lectura de memoria para la operación de lectura de memoria; seleccionar la columna de células de bits de memoria de células de bits de memoria en la matriz de memoria direccionada por la selección de columna de lectura (428); el circuito de selección de células de bits de memoria (502) caracterizado por que está configurado, además, para: generar una selección de fila de lectura/escritura (526) que indica la operación de lectura de memoria en respuesta a la operación de escritura en memoria que no está presente para la operación de lectura de memoria; y seleccionar la fila de células de bits de memoria de las células de bits de memoria en la matriz de memoria direccionada por la selección de fila de lectura (426) en respuesta a la selección de fila de lectura/escritura que indica la operación de lectura de memoria.

公开(公告)号：AU2017340249B2

公开(公告)日：2019-09-26

申请号：AU2017340249

申请日：2017-09-05

Applicant: QUALCOMM INC

Inventor： GARG MANISH

IPC: G11C7/10 ,  G11C8/08 ,  G11C8/10 ,  G11C11/418 ,  G11C11/419

Abstract: Memory systems that provide separate read and write address decoding to support simultaneous memory read and write operations are disclosed. Separating read and write address decoding can avoid circuit conflicts for a simultaneous memory read and write operation even if employing single port memory bit cells. The read and write addresses of respective read and write operations are separately decoded into read and write row and column selects driven to a memory array so that simultaneous read and write operations are not affected by each other. To avoid a circuit conflict for a simultaneous read and write operation, the memory system is configured to prioritize a write row select over a read row select to drive a row of memory bit cells in the memory array. In this manner, that write operation will always be successful regardless of whether the read and write row select are to the same row.

公开(公告)号：SG11201901324QA

公开(公告)日：2019-04-29

申请号：SG11201901324Q

申请日：2017-09-05

Applicant: QUALCOMM INC

Inventor： GARG MANISH

IPC: G11C7/10 ,  G11C8/08 ,  G11C8/10 ,  G11C11/418 ,  G11C11/419

Abstract: Memory systems that provide separate read and write address decoding to support simultaneous memory read and write operations are disclosed. Separating read and write address decoding can avoid circuit conflicts for a simultaneous memory read and write operation even if employing single port memory bit cells. The read and write addresses of respective read and write operations are separately decoded into read and write row and column selects driven to a memory array so that simultaneous read and write operations are not affected by each other. To avoid a circuit conflict for a simultaneous read and write operation, the memory system is configured to prioritize a write row select over a read row select to drive a row of memory bit cells in the memory array. In this manner, that write operation will always be successful regardless of whether the read and write row select are to the same row.

公开(公告)号：IN1829CHN2014A

公开(公告)日：2015-05-29

申请号：IN1829CHN2014

申请日：2014-03-10

Applicant: QUALCOMM INC

Inventor： PHAN MICHAEL THAITHANH ,  GARG MANISH ,  HOFF DAVID PAUL

IPC: G11C11/413

Abstract: Systems and method for reducing leakage currents and power consumption in a memory array comprising memory cells such as 8T SRAM cells. The memory array includes logic for dynamically placing a group of memory cells in the memory array in a reduced power state during sleep mode or inactive states of the group of memory cells such that leakage parts are effectively eliminated. The memory array further includes logic for dynamically enabling a selected group of the memory cells during read or write access operations on the selected memory cells wherein corresponding read or write bitlines are precharged before and after the respective rear or write operations.

公开(公告)号：AT482404T

公开(公告)日：2010-10-15

申请号：AT07757747

申请日：2007-03-01

Applicant: QUALCOMM INC

Inventor： GARG MANISH ,  HAMDAN FADI ADEL

IPC: G01R31/3185 ,  G11C29/00 ,  H03K3/037

Abstract: A dual-path, multimode sequential storage element (SSE) is described herein. In one example, the dual-path, multimode SSE comprises first and second sequential storage elements, a data input, a data output, and a selector mechanism. The first and second sequential storage elements each have an input and an output. The data input is coupled to the inputs of both sequential storage elements and is configured to accept data. The data output is coupled to the outputs of both sequential storage elements and is configured to output the data. The selector mechanism is configured to select one of the sequential storage elements for passing the data from the data input to the data output. In one example, the first sequential storage element comprises a pulse-triggered storage element and the second sequential storage element comprises a master-slave storage element.

公开(公告)号：WO2011116316A2

公开(公告)日：2011-09-22

申请号：PCT/US2011029046

申请日：2011-03-18

Applicant: QUALCOMM INC ,  PHAN MICHAEL THAITHANH ,  CHAI CHIAMING ,  GARG MANISH

Inventor： PHAN MICHAEL THAITHANH ,  CHAI CHIAMING ,  GARG MANISH

IPC: G11C7/06

CPC classification number: G11C7/02 ,  G11C7/065

Abstract: A sense amplifier circuit is implemented for suppressing Miller effect capacitive coupling. The amplifier circuit comprises a differential amplifier circuit having a first input, a first output interstitial node, a second input, a second output interstitial node, a third input to enable or disable the differential amplifier, and having an equalizer circuit coupled between the first output interstitial node and the second output interstitial node. The amplifier circuit also comprises a cross coupled latch circuit having a first latch input coupled to the first output interstitial node, a second latch input coupled to the second output interstitial node, a first latch output, and a second latch output, wherein during a first time period the first latch output and the second latch output are precharged, the differential amplifier circuit is disabled, and the equalizer circuit is enabled to suppress the Miller effect capacitive coupling on the sense amplifier inputs.

Abstract translation: 实现读出放大器电路以抑制米勒效应电容耦合。 放大器电路包括具有第一输入，第一输出空隙节点，第二输入，第二输出空隙节点，用于启用或禁用差分放大器的第三输入以及具有均衡器电路的差分放大器电路，所述均衡器电路耦合在第一输出 插页式节点和第二个输出插页式节点。 该放大器电路还包括具有耦合到第一输出间隙节点的第一锁存器输入，耦合到第二输出间隙节点的第二锁存器输入，第一锁存器输出和第二锁存器输出的交叉耦合锁存器电路，其中在第一 第一锁存器输出和第二锁存器输出被预充电时，差分放大器电路被禁止，并且均衡器电路被启用以抑制感测放大器输入端上的米勒效应电容耦合。