公开(公告)号：JP2011072009A

公开(公告)日：2011-04-07

申请号：JP2010243797

申请日：2010-10-29

Applicant: Qualcomm Inc ,  クゥアルコム・インコーポレイテッドQualcomm Incorporated

Inventor： HALTER STEVEN J

IPC: G06F11/10 ,  H03M13/29 ,  H03M13/39 ,  H03M13/45 ,  H04L1/00

CPC classification number: H03M13/3905 ,  H03M13/2957 ,  H03M13/3723 ,  H03M13/3972

Abstract: PROBLEM TO BE SOLVED: To provide a MAP decoder which operates at a high data rate.
SOLUTION: A coded signal is decoded using maximum posteriori (MAP) decoding. Several MAP engines 104 each decodes a corresponding different portion 102 of a frame 100 of symbol calculation. A tail 103 of each part is decoded into an initialization value 105 for the adjoining MAP engine 104. A resulting section 108 of soft (or hard) decision is outputted to make a decision frame 106.
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供以高数据速率操作的MAP解码器。 解决方案：使用最大后验（MAP）解码对编码信号进行解码。 几个MAP引擎104每个解码符号计算的帧100的对应的不同部分102。 每个部分的尾部103被解码为相邻的MAP引擎104的初始化值105.输出软（或硬）决定的结果部分108以作出决策框架。（C）2011年， JPO＆INPIT

公开(公告)号：JP2010016861A

公开(公告)日：2010-01-21

申请号：JP2009209398

申请日：2009-09-10

Applicant: Qualcomm Inc ,  クゥアルコム・インコーポレイテッドQualcomm Incorporated

Inventor： HALTER STEVEN J

IPC: G06F11/10 ,  H03M13/27 ,  H03M20060101 ,  H03M13/00 ,  H03M13/29 ,  H03M13/45

CPC classification number: H03M13/3905 ,  H03M13/2957 ,  H03M13/3972 ,  H03M13/6566

Abstract: PROBLEM TO BE SOLVED: To provide a memory architecture for a map decoder.
SOLUTION: The present invention is a novel and improved technique for applying particular techniques to turbo or interactive decoding techniques. A system for decoding includes a channel deinterleaver RAM for storing a block of symbol estimates and a set of S state metric calculators. Each state metric calculator is for generating a set of state metric calculators and a set of S+1 window RAMs, wherein, S of the S+1 window RAMs provide symbol estimates to the S state metric calculators. A remaining window RAM receives symbol estimates from the channel deinterleaver RAM.
COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供用于地图解码器的存储器架构。 解决方案：本发明是一种用于将特定技术应用于turbo或交互式解码技术的新颖和改进的技术。 用于解码的系统包括用于存储符号估计块和一组S状态度量计算器的信道去交织器RAM。 每个状态度量计算器用于生成一组状态度量计算器和一组S + 1窗口RAM，其中S + 1窗口RAM的S向S状态度量计算器提供符号估计。 剩余的窗口RAM从信道解交织器RAM接收符号估计。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：AU766116B2

公开(公告)日：2003-10-09

申请号：AU5563899

申请日：1999-08-13

Applicant: QUALCOMM INC

Inventor： HALTER STEVEN J

IPC: G06F11/10 ,  H03M20060101 ,  H03M13/00 ,  H03M13/27 ,  H03M13/29 ,  H03M13/45

公开(公告)号：HK1043261A1

公开(公告)日：2002-09-06

申请号：HK02104823

申请日：2002-06-28

Applicant: QUALCOMM INC

Inventor： HALTER STEVEN J

IPC: H03M13/29 ,  G06F11/10 ,  H03M13/39 ,  H03M13/45 ,  H04L1/00 ,  H03M

Abstract: A coded signal is decoded using maximum a posteriori (MAP) decoding. Several MAP engines (104) each decodes a corresponding different portion (102) of a frame (100) of symbol estimates. The tail portion (103) of each portion is decoded into an initialization value (105) for the adjoining map engine (104). The resulting sections (108) of soft (or hard) decisions are output to make a decision frame (106).

公开(公告)号：AU769694B2

公开(公告)日：2004-01-29

申请号：AU4372500

申请日：2000-03-30

Applicant: QUALCOMM INC

Inventor： HALTER STEVEN J

IPC: G06F11/10 ,  H03M13/29 ,  H03M13/39 ,  H03M13/45 ,  H04L1/00

Abstract: A coded signal is decoded using maximum a posteriori (MAP) decoding. Several MAP engines (104) each decodes a corresponding different portion (102) of a frame (100) of symbol estimates. The tail portion (103) of each portion is decoded into an initialization value (105) for the adjoining map engine (104). The resulting sections (108) of soft (or hard) decisions are output to make a decision frame (106).

公开(公告)号：AU5563899A

公开(公告)日：2000-03-06

申请号：AU5563899

申请日：1999-08-13

Applicant: QUALCOMM INC

Inventor： HALTER STEVEN J

IPC: G06F11/10 ,  H03M20060101 ,  H03M13/00 ,  H03M13/27 ,  H03M13/29 ,  H03M13/45

公开(公告)号：CA2340366A1

公开(公告)日：2000-02-24

申请号：CA2340366

申请日：1999-08-13

Applicant: QUALCOMM INC

Inventor： HALTER STEVEN J

IPC: G06F11/10 ,  H03M20060101 ,  H03M13/00 ,  H03M13/27 ,  H03M13/29 ,  H03M13/45

Abstract: The present invention is a novel and improved technique for decoding techniq ue with particular application to turbo, or iterative, coding techniques. In accordance with one embodiment of the invention, a system for decoding includes a channel deinterleaver RAM for storing a block of symbol estimates , a set of S state metric calculators and a set of S+1 window RAMs. Each state metric calculator is for generating a set of state metric calculations, wherein, S of said S+1 window RAMs provide symbol estimates to said S state metric calculators. A remaining window RAM receives symbol estimates from sa id channel deinterleaver RAM.

公开(公告)号：CA2422328C

公开(公告)日：2010-03-30

申请号：CA2422328

申请日：2001-09-12

Applicant: QUALCOMM INC

Inventor： HALTER STEVEN J

IPC: H03K23/64 ,  H03K23/68 ,  H03L7/16

Abstract: A counter for synthesizing clock signals with minimal jitter. The inventive counter has a first counter stage; a look-ahead circuit input connected to said first counter stage; and a selection circuit for choosing between an output of said first counter stage and an output of said look-ahead circuit as an output of said counter. In the specific embodiment, the first counter stage is adapted to receive a first clock signal having a frequency of N cycles per second and output a second clock signal having a frequency of M cycles per second. The first counter stage includes an accumulator having a rollover point at which an instantaneous count thereof exceeds the value of N-M. The look-ahead circuit determines for a present clock cycle the rollover point for a preceding clock cycle. The look-ahead circuit is a second counter stage adapted to ascertain whether the rising edge or the trailing edge of the second clock signal is closer to the rollover point and output an indication with respect thereto.

公开(公告)号：MXPA01009713A

公开(公告)日：2002-09-30

申请号：MXPA01009713

申请日：2000-03-30

Applicant: QUALCOMM INC

Inventor： HALTER STEVEN J

IPC: H03M13/29 ,  G06F11/10 ,  H03M13/39 ,  H03M13/45 ,  H04L1/00

Abstract: Se descodifica una senal codificada utilizando una descodificacion a posteriori maxima (MAP). Varios motores de MAP (104) descodifican cada uno una porcion diferente correspondiente (102) de una trama (100) de estimados de simbolo. La porcion de, cola (103) de cada porcion se decodifica en un valor de inicializacion (105) para el motor de map adjunto (104). Las secciones resultantes (108) de decisiones suaves (o duras) se entregan como, salida para hacer una trama de decision (106).

公开(公告)号：ES2347309T3

公开(公告)日：2010-10-27

申请号：ES99942209

申请日：1999-08-13

Applicant: QUALCOMM INC

Inventor： HALTER STEVEN J

IPC: G06F11/10 ,  H03M13/39 ,  H03M20060101 ,  H03M13/00 ,  H03M13/27 ,  H03M13/29 ,  H03M13/45

Abstract: Un sistema para llevar a cabo una decodificación de la probabilidad máxima a posteriori en ventana desplazable, en lo sucesivo denominada MAP, comprendiendo la decodificación: a) una RAM (160) de desentrelazado de canal para almacenar un bloque de estimaciones de símbolos; b) un total de S calculadores (272, 274) de métricas de estado, siendo cada calculador de métricas de estado para generar un conjunto de cálculos métricos de estado, en el que dichos calculadores (272, 274) de métricas de estado procesan datos en ventanas iguales o menores que el tamaño de una RAM de ventana; c) un conjunto de S+1 RAM (230A-D) de ventana, en el que S de dichas S+1 RAM de ventana proporcionan estimaciones de símbolos a dichos S calculadores de métricas de estado, y una RAM restante de ventana recibe estimaciones de símbolos desde dicha RAM (160) de desentrelazado de canal.