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    Fm transmitter and non-fm receiver integrated on single chip
    1.
    发明专利
    Fm transmitter and non-fm receiver integrated on single chip 有权
    FM发射机和非FM收音机集成在单芯片上

    公开(公告)号：JP2013219772A

    公开(公告)日：2013-10-24

    申请号：JP2013084527

    申请日：2013-04-15

    Applicant: Qualcomm Inc ,  クゥアルコム・インコーポレイテッドQualcomm Incorporated

    Inventor： LIN I-HSIANG ,  PAN TZU-WANG ,  ZENG YI

    IPC: H04B1/40 ,  H04B1/04

    CPC classification number: H04B1/525

    Abstract: PROBLEM TO BE SOLVED: To efficiently implement a frequency modulation (FM) transmitter and a non-FM receiver on the same IC chip.SOLUTION: The FM transmitter includes a digital FM modulator, a lowpass filter, an amplifier, and an LC tank circuit. The digital FM modulator receives a digital input signal, performs FM modulation with the digital input signal, and provides a digital FM signal. The lowpass filter filters the digital FM signal and provides a filtered FM signal. The amplifier amplifies the filtered FM signal and provides an output FM signal. The LC tank circuit filters the output FM signal. The digital FM modulator performs FM modulation by changing a variable divider ratio of a multi-modulus divider within a PLL. A delta-sigma modulator receives the digital input signal and generates a modulator output signal used to obtain the variable divider ratio.

    Abstract translation: 要解决的问题：在同一个IC芯片上有效实现调频（FM）发射机和非FM接收机。解决方案：FM发射机包括数字FM调制器，低通滤波器，放大器和LC电路 。 数字FM调制器接收数字输入信号，用数字输入信号进行FM调制，并提供数字FM信号。 低通滤波器对数字FM信号进行滤波，并提供滤波后的FM信号。 放大器放大滤波的FM信号并提供输出FM信号。 LC振荡电路对输出的FM信号进行滤波。 数字FM调制器通过改变PLL内的多模式分频器的可变分频比来执行FM调制。 Δ-Σ调制器接收数字输入信号并产生用于获得可变分频比的调制器输出信号。

    クロッククリーンアップ位相ロックループ（ＰＬＬ）
    2.
    发明专利
    クロッククリーンアップ位相ロックループ（ＰＬＬ） 审中-公开

    公开(公告)号：JP2015092671A

    公开(公告)日：2015-05-14

    申请号：JP2014228450

    申请日：2014-11-10

    Applicant: QUALCOMM INC

    Inventor： LIN I-HSIANG ,  ROGER BROCKENBROUGH

    IPC: H03L7/22 ,  H04B1/16 ,  H04L7/04

    Abstract: 【課題】スプリアスを低減し受信機性能を向上するクロッククリーンアップ位相ロックループ(PLL)を提供する。【解決手段】集積回路(RFIC)210はPLL240及びアナログ/デジタルコンバータ(ADC)230を含む。PLL240は、フラクショナル分周比で生成され、突発的周波数ジャンプによるスプリアスを有する第1クロック信号CLK1を受信する。第1クロック信号CLK1は、集積回路外部のフラクショナルNの周波数シンセサイザ260によって生成される。PLL240は、整数の分周比で、低減されたスプリアスを有する第2クロック信号CLK2を生成する。ADC230は、第2クロック信号CLK2に基づいてアナログベースバンド信号をデジタル化してデジタルサンプルを供給する。集積回路210は更に、低ノイズ増幅器(LNA)222を有し、集積回路210の基板を介して結合するより小さいスプリアスを観測する。【選択図】図2

    OVERLAPPING, TWO-SEGMENT CAPACITOR BANK FOR VCO FREQUENCY TUNING
    7.
    发明申请
    OVERLAPPING, TWO-SEGMENT CAPACITOR BANK FOR VCO FREQUENCY TUNING 审中-公开
    用于VCO频率调谐的两部分电容器

    公开(公告)号：WO2010129925A2

    公开(公告)日：2010-11-11

    申请号：PCT/US2010034129

    申请日：2010-05-07

    Applicant: QUALCOMM INC ,  ZENG YI ,  PAN TZU-WANG ,  LIN I-HSIANG

    Inventor： ZENG YI ,  PAN TZU-WANG ,  LIN I-HSIANG

    IPC: H03B5/12

    CPC classification number: H03B5/1228 ,  H03B5/1212 ,  H03B5/1253 ,  H03B5/1265 ,  H03B5/1293

    Abstract: A VCO (for example, in an FM receiver) includes an LC resonant tank. The LC resonant tank includes a coarse tuning capacitor bank and a fine tuning capacitor bank. The coarse tuning capacitor bank contains a plurality of digitally controlled coarse tuning capacitor elements, each providing a first capacitance value when active. The fine tuning capacitor bank contains a plurality of digitally controlled fine tuning capacitor elements, each providing a second capacitance value when active. To address the practical problem of capacitor mismatch, capacitance overlap throughout the VCO tuning range is created by selecting the first and second capacitance values such that the capacitance value of the fine capacitor bank is greater than the first capacitance value when all of the digitally controlled fine tuning capacitor elements of the fine capacitor bank are active.

    Abstract translation: VCO（例如，在FM接收机中）包括LC谐振回路。 LC谐振槽包括一个粗调谐电容器组和一个微调电容器组。 粗调谐电容器组包含多个数字控制的粗调电容器元件，每个主调制电容器元件在有源时提供第一电容值。 微调电容器组包含多个数字控制的微调电容器元件，每个微调电容器元件在有源时提供第二电容值。 为了解决电容器失配的实际问题，通过选择第一和第二电容值来创建整个VCO调谐范围内的电容重叠，使得当全部数字控制的精细时，精细电容器组的电容值大于第一电容值 精细电容器组的调谐电容器元件是有效的。

    FM TRANSMITTER AND NON-FM RECEIVER INTEGRATED ON SINGLE CHIP
    8.
    发明申请
    FM TRANSMITTER AND NON-FM RECEIVER INTEGRATED ON SINGLE CHIP 审中-公开
    FM发射机和非FM收音机集成在单芯片上

    公开(公告)号：WO2010059872A2

    公开(公告)日：2010-05-27

    申请号：PCT/US2009065213

    申请日：2009-11-19

    Applicant: QUALCOMM INC ,  LIN I-HSIANG ,  PAN TZU-WANG ,  ZENG YI

    Inventor： LIN I-HSIANG ,  PAN TZU-WANG ,  ZENG YI

    IPC: H03D5/00

    CPC classification number: H04B1/525

    Abstract: Exemplary embodiments include a frequency modulation (FM) transmitter and a non-FM receiver, which may be implemented on the same IC chip. The FM transmitter may include a digital FM modulator, a lowpass filter, an amplifier, and an LC tank circuit. The digital FM modulator may receive a digital input signal, perform FM modulation with the digital input signal, and provide a digital FM signal. The lowpass filter may filter the digital FM signal and provide a filtered FM signal. The amplifier may amplify the filtered FM signal and provide an output FM signal. The LC tank circuit may filter the output FM signal. The digital FM modulator may perform FM modulation by changing a variable divider ratio of a multi-modulus divider within a PLL. A delta-sigma modulator may receive the digital input signal and generate a modulator output signal used to obtain the variable divider ratio.

    Abstract translation: 示例性实施例包括可以在同一IC芯片上实现的调频（FM）发射机和非FM接收机。 FM发射机可以包括数字FM调制器，低通滤波器，放大器和LC电路。 数字FM调制器可以接收数字输入信号，使用数字输入信号执行FM调制，并提供数字FM信号。 低通滤波器可以对数字FM信号进行滤波并提供滤波后的FM信号。 放大器可以放大经滤波的FM信号并提供输出FM信号。 LC振荡电路可以对输出的FM信号进行滤波。 数字FM调制器可以通过改变PLL内的多模式分频器的可变分频比来执行FM调制。 Δ-Σ调制器可以接收数字输入信号并产生用于获得可变分频比的调制器输出信号。

    RFIC CONFIGURATION FOR REDUCED ANTENNA TRACE LOSS
    9.
    发明申请
    RFIC CONFIGURATION FOR REDUCED ANTENNA TRACE LOSS 审中-公开
    减少天线跟踪损失的RFIC配置

    公开(公告)号：WO2014093716A3

    公开(公告)日：2014-10-30

    申请号：PCT/US2013074823

    申请日：2013-12-12

    Applicant: QUALCOMM INC

    Inventor： LIN I-HSIANG ,  XIONG ZHIJIE ,  KRISHNAMOORTHY SESHAGIRI ,  KO JIN-SU ,  AKULA PRASHANTH ,  ZHAO LIANG ,  WANG KEVIN HSI HUAI ,  ZHAO DESONG

    IPC: H04B1/00

    CPC classification number: H04B1/0064

    Abstract: An RFIC configuration for reduced antenna trace loss is disclosed. In an exemplary embodiment, an apparatus includes a primary RFIC and a secondary RFIC that is configured to receive analog signals from at least two antennas. The secondary RFIC is configured to process selected analog signals received from at least one antenna to generate an analog output that is input to the primary RFIC.

    Abstract translation: 公开了一种用于降低天线轨迹损耗的RFIC配置。 在示例性实施例中，装置包括主RFIC和辅助RFIC，其被配置为从至少两个天线接收模拟信号。 辅助RFIC被配置为处理从至少一个天线接收的所选择的模拟信号，以产生被输入到主RFIC的模拟输出。

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