公开(公告)号：JP2013101638A

公开(公告)日：2013-05-23

申请号：JP2012277649

申请日：2012-12-20

Applicant: Qualcomm Inc ,  クゥアルコム・インコーポレイテッドQualcomm Incorporated

Inventor： ERICH PLONDKE ,  ROBERT ALAN LESTER ,  LUCIAN CODRESCU ,  MUHAMMAD AHMED

IPC: G06F9/32 ,  G06F9/30 ,  G06F9/45

CPC classification number: G06F9/30149 ,  G06F9/325 ,  G06F9/3853 ,  G06F9/3885

Abstract: PROBLEM TO BE SOLVED: To provide a method and device for encoding information regarding a hardware loop of a set of packets.SOLUTION: Each packet includes a plurality of instructions. The information regarding the hardware loop is encoded into one or more bits of at least one instruction in the set of packets. The information indicates whether or not a packet is an end packet of the loop. Information regarding two hardware loops is encoded. That is, information regarding a first loop is encoded into an instruction at a first predetermined position in each packet and information regarding a second loop is encoded into an instruction at a second predetermined position in each packet. End instruction information is encoded into an instruction not having encoded loop information at the same bit positions reserved for the encoded loop information. The end instruction information indicates whether or not the instruction is the last instruction of a packet and the length of a packet.

Abstract translation: 要解决的问题：提供一种用于编码关于一组分组的硬件循环的信息的方法和装置。 解决方案：每个分组包括多个指令。 关于硬件循环的信息被编码成该组数据包中的至少一个指令的一个或多个位。 该信息指示分组是否是循环的结束分组。 关于两个硬件循环的信息被编码。 也就是说，关于第一循环的信息被编码为每个分组中的第一预定位置处的指令，并且关于第二循环的信息被编码为每个分组中的第二预定位置处的指令。 结束指令信息被编码为在编码的环路信息保留的相同位位置处不具有编码环路信息的指令。 结束指令信息指示指令是否是分组的最后指令和分组的长度。 版权所有（C）2013，JPO＆INPIT

公开(公告)号：JP2013239183A

公开(公告)日：2013-11-28

申请号：JP2013125463

申请日：2013-06-14

Applicant: Qualcomm Inc ,  クゥアルコム・インコーポレイテッドQualcomm Incorporated

Inventor： SURESH K VENKUMAHANTI ,  LUCIAN CODRESCU ,  LIN WANG

IPC: G06F12/10 ,  G06F9/38 ,  G06F12/08

CPC classification number: G06F9/3851 ,  G06F9/34 ,  G06F9/3824 ,  G06F9/3828 ,  G06F9/3885

Abstract: PROBLEM TO BE SOLVED: To provide a method for reducing power consumption accompanying tag array lookup operations and translation look-aside buffer (TLB) lookup operations of a cache.SOLUTION: Tag array lookup operations may be selectively skipped when a second address of a second instruction is associated with the same cache line as a first address of a first instruction. Tag array information determined in a previous lookup operation associated with the first address may be reused. Further, TLB lookup operations are selectively skipped. The method includes: examining a carry bit of an adder of a data unit in order to determine whether the second address has crossed a boundary of a cache line associated with a multi-way cache; and examining a second carry bit of the adder in order to determine whether the second address has crossed a boundary of a page.

Abstract translation: 要解决的问题：提供一种降低与标签阵列查找操作和缓存的翻译后备缓冲器（TLB）查找操作相关联的功耗的方法。解决方案：当第二个地址的第二个地址 指令与与第一指令的第一地址相同的高速缓存行相关联。 在与第一地址相关联的先前查找操作中确定的标签阵列信息可以被重用。 此外，选择性地跳过TLB查找操作。 该方法包括：检查数据单元的加法器的进位位，以便确定第二地址是否已经跨越与多路高速缓存相关联的高速缓存行的边界; 以及检查加法器的第二进位位，以便确定第二地址是否超过了页的边界。

公开(公告)号：JP2013232210A

公开(公告)日：2013-11-14

申请号：JP2013128940

申请日：2013-06-19

Applicant: Qualcomm Inc ,  クゥアルコム・インコーポレイテッドQualcomm Incorporated

Inventor： AJAY A INGLE ,  ERICH J PLONDKE ,  LUCIAN CODRESCU

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/0808 ,  G06F12/121 ,  G06F2212/1016 ,  Y02D10/13

Abstract: PROBLEM TO BE SOLVED: To provide a computer readable storage medium for determining a cache line to replace.SOLUTION: A system 300 includes a cache comprising a plurality of cache lines. When an instruction is executed by a processor, the system causes the processor to receive an index value included in an invalidate-cache-by-index instruction, a coded way value, and an output value of an incrementer 120 and, in response to the reception of the invalidate-cache-by-index instruction, to assign the index value as a value of an identifier 114. The value of the identifier indicates a cache line for replacement.

Abstract translation: 要解决的问题：提供用于确定要替换的高速缓存行的计算机可读存储介质。解决方案：系统300包括包括多个高速缓存行的高速缓存。 当处理器执行指令时，系统使处理器接收包括在无效缓存逐个索引指令，编码方式值和递增器120的输出值中的索引值，并且响应于 接收无效缓存逐个索引指令，以将索引值分配为标识符114的值。标识符的值指示用于替换的高速缓存行。

公开(公告)号：JP2013242892A

公开(公告)日：2013-12-05

申请号：JP2013142053

申请日：2013-07-05

Applicant: Qualcomm Inc ,  クゥアルコム・インコーポレイテッドQualcomm Incorporated

Inventor： MAO ZENG ,  LUCIAN CODRESCU

IPC: G06F9/30 ,  G06F9/34

CPC classification number: G06F9/30032 ,  G06F9/30025 ,  G06F9/30036

Abstract: PROBLEM TO BE SOLVED: To combine corresponding half word units from multiple register units by carrying out a single instruction.SOLUTION: An instruction is carried out to: combine corresponding half word units from source register units; input the half word units into respective portions of a resulting destination register unit; identify the predetermined source register units; and retrieve corresponding most significant half word units and associated data from the identified register units. The retrieved half word units are combined and input into a corresponding most significant portion of the resulting destination register unit. Similarly, corresponding least significant half word units and associated data are retrieved from the identified register units; and the retrieved half word units are combined and input into a corresponding least significant portion of the resulting register unit. Finally, the resulting destination register unit is stored in the register file structure for further processing.

Abstract translation: 要解决的问题：通过执行单个指令来组合来自多个寄存器单元的对应的半字单元。解决方案：执行指令，以组合来自源寄存器单元的对应的半字单位; 将半字单元输入到所得到的目的地寄存器单元的相应部分中; 识别预定的源寄存器单元; 并从所识别的寄存器单元中检索对应的最高有效半字单元和相关数据。 所检索的半字单元被组合并输入到所得到的目标寄存器单元的对应的最高有效部分。 类似地，从所识别的寄存器单元检索相应的最低有效半字单元和相关联的数据; 并且将所检索的半字单元组合并输入到所得到的寄存器单元的对应的最低有效部分。 最后，生成的目标寄存器单元被存储在寄存器堆栈结构中用于进一步处理。

公开(公告)号：JP2013145568A

公开(公告)日：2013-07-25

申请号：JP2013034561

申请日：2013-02-25

Applicant: Qualcomm Inc ,  クゥアルコム・インコーポレイテッドQualcomm Incorporated

Inventor： LUCIAN CODRESCU ,  ERICH J PLONDKE ,  SURESH K VENKUMAHANTI

IPC: G06F9/52 ,  G06F9/48 ,  G06F12/10

CPC classification number: G06F9/526 ,  G06F9/30083 ,  G06F9/30101 ,  G06F12/1027 ,  G06F2209/522 ,  Y02D10/13

Abstract: PROBLEM TO BE SOLVED: To provide a multi-thread processor having a lock indicator for performing the quick lock and unlock of a shared resource, and for reducing power consumption.SOLUTION: The method includes: receiving a TLB (Translation Look-aside Buffer) mistake event relating to the thread of a multi-thread processor 102; checking a TLB lock indicator 110; allowing a thread 112 to perform access to an exceptional handler 122 relating to a TLB 108 when the TLB lock indicator 110 is unlocked; and putting the thread 112 in a sleep state when the TLB lock indicator 110 is locked.

Abstract translation: 要解决的问题：提供一种具有用于执行共享资源的快速锁定和解锁的锁定指示符并且用于降低功耗的多线程处理器。解决方案：该方法包括：接收TLB（翻译后备缓冲器） 与多线程处理器102的线程有关的错误事件; 检查TLB锁定指示器110; 允许线程112在TLB锁定指示器110解锁时执行与TLB 108有关的异常处理器122的访问; 并且当TLB锁定指示器110被锁定时将线程112置于睡眠状态。

公开(公告)号：JP2012178165A

公开(公告)日：2012-09-13

申请号：JP2012089195

申请日：2012-04-10

Applicant: Qualcomm Inc ,  クゥアルコム・インコーポレイテッドQualcomm Incorporated

Inventor： LUCIAN CODRESCU ,  WILLIAM C ANDERSON ,  SURESH VENKUMAHANTI ,  LOUIS ACHIELE GIANNINI ,  MANOGIKMER PILA ,  CHEN XUFENG

IPC: G06F11/28

CPC classification number: G06F11/362 ,  G06F11/3656

Abstract: PROBLEM TO BE SOLVED: To debug a core processor in association with a multi-threaded digital signal processor.SOLUTION: Writing a stuffing instruction in a debugging process registry and writing a stuffing command in a debugging process command register identify a predetermined thread of the multi-threaded digital signal processor to execute the stuffing instruction. An instruction stuffing process issues a debugging process control resume command during a predetermined execution stage on the predetermined thread, and instructs the core processor to execute the stuffing instruction during the debugging process. Here, the core processor is capable of executing the stuffed instruction in association with the core processor process and the debugging process.

Abstract translation: 要解决的问题：调试与多线程数字信号处理器相关联的核心处理器。 解决方案：在调试过程注册表中写入填充指令并在调试过程命令寄存器中写入填充命令来标识多线程数字信号处理器的预定线程以执行填充指令。 指令填充处理在预定线程的预定执行阶段发出调试过程控制恢复命令，并且指示核心处理器在调试过程中执行填充指令。 这里，核心处理器能够与核心处理器处理和调试过程相关联地执行填充指令。 版权所有（C）2012，JPO＆INPIT

公开(公告)号：BR112018076270A2

公开(公告)日：2019-03-26

申请号：BR112018076270

申请日：2017-06-06

Applicant: QUALCOMM INC

Inventor： ERIC WAYNE MAHURIN ,  JAKUB PAWAL GOLAB ,  LUCIAN CODRESCU

IPC: G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F12/00

Abstract: sistemas e métodos se referem a operações de memória eficientes. uma operação de coleta de instrução única e múltiplos dados (simd) é implementada com um armazenador de resultados de coleta localizado dentro de ou perto da memória, para receber ou coletar múltiplos elementos de dados a partir de múltiplas localizações ortogonais em uma memória, e uma vez que o armazenador de resultado de coleta está completo, os dados coletados são transferidos para um registro de processador. uma operação de cópia simd é realizada pela execução de duas ou mais instruções para copiar os múltiplos elementos de dados a partir de múltiplos endereços fonte ortogonais para múltiplos endereços de destino correspondentes dentro da memória, sem uma cópia intermediária para um registro de processador. dessa forma, as operações de memória são realizadas em um modo de fundo sem instrução por parte do processador.

公开(公告)号：JP2014238859A

公开(公告)日：2014-12-18

申请号：JP2014150573

申请日：2014-07-24

Applicant: クアルコム,インコーポレイテッド ,  Qualcomm Inc

Inventor： LUCIAN CODRESCU ,  ERICH JAMES PLONDKE ,  AJAY ANANT INGLE ,  SURESH K VENKUMAHANTI ,  CHARLES JOSEPH TABONY

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3853 ,  G06F9/30149

Abstract: 【課題】階層型の超長命令語(VLIW)パケットを処理するシステムおよび方法、命令を処理する方法を提供する。【解決手段】命令の階層型VLIWパケット108を受信するステップ102と、命令が単一の命令110、112であるか、または、命令が複数のサブ命令116、118を含むサブパケット114を含むかを決定するために、パケット108から命令を復号するステップ104とを含む。命令がサブパケット114を含むことを決定したことに応答して、サブ命令116、118の各々を実行するステップ106も含む。【選択図】図1

Abstract translation: 要解决的问题：提供一种处理分级非常长的指令字（VLIW）分组的系统和方法以及处理指令的方法。解决方案：一种方法包括：接收102指令的分层VLIW分组108，以及解码104指令 从分组108确定该指令是单个指令110,112还是该指令是否包括包括多个子指令116,118的子分组114.该方法还包括响应于确定该指令包括 子分组114，执行106个子指令116,118中的每一个。

公开(公告)号：JP2013218709A

公开(公告)日：2013-10-24

申请号：JP2013103471

申请日：2013-05-15

Applicant: Qualcomm Inc ,  クゥアルコム・インコーポレイテッドQualcomm Incorporated

Inventor： LUCIAN CODRESCU ,  ERICH PLONDKE ,  MAO ZENG

IPC: G06F9/30

CPC classification number: G06F9/30032 ,  G06F9/30036 ,  G06F9/30112

Abstract: PROBLEM TO BE SOLVED: To provide a method and system to combine multiple register units within a microprocessor, such as a digital signal processor.SOLUTION: A first register unit 510 and a second register unit 520 are retrieved from a register file structure within a processing unit, the first register unit and the second register unit being non-adjacently located within the register file structure. The first register unit and the second register unit are combined during execution of a single instruction to form a resulting register unit 530. Finally, the resulting register unit is stored within the register file structure for further processing. Alternatively, a first half word unit is retrieved from the first register unit and a second half word unit is retrieved from the second register unit. The first half word unit and the second half word unit are further input into corresponding high and low portions of the resulting register unit to form the resulting register unit during execution of a single instruction. Finally, the resulting register unit is stored within the register file structure for further processing.

Abstract translation: 要解决的问题：提供一种方法和系统，以组合微处理器内的多个寄存器单元，例如数字信号处理器。解决方案：第一寄存器单元510和第二寄存器单元520从处理中的寄存器堆栈结构检索 单元，第一寄存器单元和第二寄存器单元不相邻地位于寄存器堆栈结构内。 在执行单个指令期间组合第一寄存器单元和第二寄存器单元以形成结果寄存器单元530.最后，所得到的寄存器单元存储在寄存器堆栈结构中用于进一步处理。 或者，从第一寄存器单元检索第一半字单元，并从第二寄存器单元检索第二半字单元。 第一半字单元和第二半字单元进一步输入到所得寄存器单元的对应的高和低部分中，以在单个指令的执行期间形成结果寄存器单元。 最后，所得到的寄存器单元被存储在寄存器堆栈结构中以便进一步处理。

公开(公告)号：JP2013175218A

公开(公告)日：2013-09-05

申请号：JP2013087516

申请日：2013-04-18

Applicant: Qualcomm Inc ,  クゥアルコム・インコーポレイテッドQualcomm Incorporated

Inventor： LUCIAN CODRESCU ,  ERICH PLONDKE ,  TAYLOR SIMPSON

IPC: G06F9/32 ,  G06F9/38 ,  G06F17/16

CPC classification number: G06F9/30101 ,  G06F9/30021 ,  G06F9/30094 ,  G06F9/3885

Abstract: PROBLEM TO BE SOLVED: To provide an improved system and method for processing vector operations taking into account scalar conditions.SOLUTION: A processor device is disclosed that includes a register file with a combined condition code register for scalar and vector operations. The processor device utilizes the combined condition code register for scalar and vector operations. Further, a comparison operation can store resulting bits in the combined condition code register and a conditional operation can utilize the combined condition code register bits for evaluating a condition.

Abstract translation: 要解决的问题：提供一种改进的系统和方法，用于考虑标量条件来处理向量操作。解决方案：公开了一种处理器设备，其包括具有用于标量和向量操作的组合条件代码寄存器的寄存器文件。 处理器设备利用组合条件码寄存器进行标量和矢量操作。 此外，比较操作可以将结果比特存储在组合条件码寄存器中，并且条件操作可以利用组合条件码寄存器比特来评估条件。