-
公开(公告)号：CA2380984C
公开(公告)日：2013-04-02
申请号：CA2380984
申请日：2000-08-30
Applicant: QUALCOMM INC
Inventor： LUPIN EDWARD D , SINDHUSHAYANA NAGABHUSHANA T
Abstract: A novel method and apparatus for generating PN sequences with an arbitrary number of bits, where the number of bits is provided in parallel with each clock pulse is described. This allows the sequences to be generated at high speed when needed, and allows parallel processing in the acquisition and demodulation processes. In the invention, the initial values of states are loaded into registers of a parallel PN generator, which immediately generates the next n bits of the PN sequence, where n is an arbitrary number dependent on performance required. Then, a first sub-part of the PN generator (406) of the present invention receives the present state of the PN generator (406) and outputs the state of the PN generator (406)n bits in the future.
-
公开(公告)号：NO20020966A
公开(公告)日：2002-02-27
申请号：NO20020966
申请日：2002-02-27
Applicant: QUALCOMM INC
Inventor： LUPIN EDWARD D , SINDHUSHAYANA NAGABHUSHANA T
CPC classification number: G06F7/584
-
公开(公告)号：AT308076T
公开(公告)日：2005-11-15
申请号：AT00959687
申请日：2000-08-30
Applicant: QUALCOMM INC
Inventor： LUPIN EDWARD D , SINDHUSHAYANA NAGABHUSHANA T
Abstract: The invention presented is a novel method and apparatus for generating PN sequences with an arbitrary number of bits, where the number of bits is provided in parallel with each clock pulse. This allows the sequences to be generated at high speed when needed, and allows parallel processing in the acquisition and demodulation processes. In the invention, the initial values of states are loaded into registers of a parallel PN generator, which immediately generates the next n bits of the PN sequence, where n is an arbitrary number dependent on performance required. Then, a first sub-part of the PN generator of the present invention receives the present state of the PN generator and outputs the state of the PN generator n bits in the future. The output of this first sub-part is then provided to a second sub-part of the generator, which generates the next n bits of the PN sequence. In this fashion, the entire PN sequence can be continuously generated. The PN generator also contains a control processor, coordinating co-operation between sub-systems.
-
公开(公告)号：NO20020966L
公开(公告)日：2002-02-27
申请号：NO20020966
申请日：2002-02-27
Applicant: QUALCOMM INC
Inventor： LUPIN EDWARD D , SINDHUSHAYANA NAGABHUSHANA T
Abstract: The invention presented is a novel method and apparatus for generating PN sequences with an arbitrary number of bits, where the number of bits is provided in parallel with each clock pulse. This allows the sequences to be generated at high speed when needed, and allows parallel processing in the acquisition and demodulation processes. In the invention, the initial values of states are loaded into registers of a parallel PN generator, which immediately generates the next n bits of the PN sequence, where n is an arbitrary number dependent on performance required. Then, a first sub-part of the PN generator of the present invention receives the present state of the PN generator and outputs the state of the PN generator n bits in the future. The output of this first sub-part is then provided to a second sub-part of the generator, which generates the next n bits of the PN sequence. In this fashion, the entire PN sequence can be continuously generated. The PN generator also contains a control processor, coordinating co-operation between sub-systems.
-
公开(公告)号：AU781309B2
公开(公告)日：2005-05-12
申请号：AU7096500
申请日：2000-08-30
Applicant: QUALCOMM INC
Inventor： LUPIN EDWARD D , SINDHUSHAYANA NAGABHUSHANA T
Abstract: The invention presented is a novel method and apparatus for generating PN sequences with an arbitrary number of bits, where the number of bits is provided in parallel with each clock pulse. This allows the sequences to be generated at high speed when needed, and allows parallel processing in the acquisition and demodulation processes. In the invention, the initial values of states are loaded into registers of a parallel PN generator, which immediately generates the next n bits of the PN sequence, where n is an arbitrary number dependent on performance required. Then, a first sub-part of the PN generator of the present invention receives the present state of the PN generator and outputs the state of the PN generator n bits in the future. The output of this first sub-part is then provided to a second sub-part of the generator, which generates the next n bits of the PN sequence. In this fashion, the entire PN sequence can be continuously generated. The PN generator also contains a control processor, coordinating co-operation between sub-systems.
-
Patent Agency Ranking
公开(公告)号：HK1047176A1
公开(公告)日：2003-02-07
申请号：HK02108771
申请日：2002-12-03
Applicant: QUALCOMM INC
Inventor： LUPIN EDWARD D , SINDHUSHAYANA NAGABUSHANA T
IPC: G06F20060101 , G06F7/58 , H03K3/84
Abstract: The invention presented is a novel method and apparatus for generating PN sequences with an arbitrary number of bits, where the number of bits is provided in parallel with each clock pulse. This allows the sequences to be generated at high speed when needed, and allows parallel processing in the acquisition and demodulation processes. In the invention, the initial values of states are loaded into registers of a parallel PN generator, which immediately generates the next n bits of the PN sequence, where n is an arbitrary number dependent on performance required. Then, a first sub-part of the PN generator of the present invention receives the present state of the PN generator and outputs the state of the PN generator n bits in the future. The output of this first sub-part is then provided to a second sub-part of the generator, which generates the next n bits of the PN sequence. In this fashion, the entire PN sequence can be continuously generated. The PN generator also contains a control processor, coordinating co-operation between sub-systems.
-
公开(公告)号：AU7096500A
公开(公告)日：2001-03-26
申请号：AU7096500
申请日：2000-08-30
Applicant: QUALCOMM INC
Inventor： LUPIN EDWARD D , SINDHUSHAYANA NAGABHUSHANA T
Abstract: The invention presented is a novel method and apparatus for generating PN sequences with an arbitrary number of bits, where the number of bits is provided in parallel with each clock pulse. This allows the sequences to be generated at high speed when needed, and allows parallel processing in the acquisition and demodulation processes. In the invention, the initial values of states are loaded into registers of a parallel PN generator, which immediately generates the next n bits of the PN sequence, where n is an arbitrary number dependent on performance required. Then, a first sub-part of the PN generator of the present invention receives the present state of the PN generator and outputs the state of the PN generator n bits in the future. The output of this first sub-part is then provided to a second sub-part of the generator, which generates the next n bits of the PN sequence. In this fashion, the entire PN sequence can be continuously generated. The PN generator also contains a control processor, coordinating co-operation between sub-systems.
-
公开(公告)号：CA2380984A1
公开(公告)日：2001-03-08
申请号：CA2380984
申请日：2000-08-30
Applicant: QUALCOMM INC
Inventor： SINDHUSHAYANA NAGABHUSHANA T , LUPIN EDWARD D
Abstract: A novel method and apparatus for generating PN sequences with an arbitrary number of bits, where the number of bits is provided in parallel with each clock pulse is described. This allows the sequences to be generated at high speed when needed, and allows parallel processing in the acquisition and demodulation processes. In the invention, the initial values of states are loaded into registers of a parallel PN generator, which immediately generate s the next n bits of the PN sequence, where n is an arbitrary number dependent on performance required. Then, a first sub-part of the PN generator (406) of the present invention receives the present state of the PN generator (406) a nd outputs the state of the PN generator (406)n bits in the future.
-
公开(公告)号：NO325775B1
公开(公告)日：2008-07-14
申请号：NO20020966
申请日：2002-02-27
Applicant: QUALCOMM INC
Inventor： SINDHUSHAYANA NAGABHUSHANA T , LUPIN EDWARD D
Abstract: The invention presented is a novel method and apparatus for generating PN sequences with an arbitrary number of bits, where the number of bits is provided in parallel with each clock pulse. This allows the sequences to be generated at high speed when needed, and allows parallel processing in the acquisition and demodulation processes. In the invention, the initial values of states are loaded into registers of a parallel PN generator, which immediately generates the next n bits of the PN sequence, where n is an arbitrary number dependent on performance required. Then, a first sub-part of the PN generator of the present invention receives the present state of the PN generator and outputs the state of the PN generator n bits in the future. The output of this first sub-part is then provided to a second sub-part of the generator, which generates the next n bits of the PN sequence. In this fashion, the entire PN sequence can be continuously generated. The PN generator also contains a control processor, coordinating co-operation between sub-systems.
-
公开(公告)号：BR0013633A
公开(公告)日：2002-07-02
申请号：BR0013633
申请日：2000-08-30
Applicant: QUALCOMM INC
Inventor： LUPIN EDWARD D , SINDHUSHAYANA NAGABHUSHANA T
Abstract: The invention presented is a novel method and apparatus for generating PN sequences with an arbitrary number of bits, where the number of bits is provided in parallel with each clock pulse. This allows the sequences to be generated at high speed when needed, and allows parallel processing in the acquisition and demodulation processes. In the invention, the initial values of states are loaded into registers of a parallel PN generator, which immediately generates the next n bits of the PN sequence, where n is an arbitrary number dependent on performance required. Then, a first sub-part of the PN generator of the present invention receives the present state of the PN generator and outputs the state of the PN generator n bits in the future. The output of this first sub-part is then provided to a second sub-part of the generator, which generates the next n bits of the PN sequence. In this fashion, the entire PN sequence can be continuously generated. The PN generator also contains a control processor, coordinating co-operation between sub-systems.
-
-
-
-
-
-
-
-
-
Search Results
12
records
(took 0.022 seconds)
