公开(公告)号：JP2012135015A

公开(公告)日：2012-07-12

申请号：JP2012030620

申请日：2012-02-15

Applicant: Qualcomm Inc ,  クゥアルコム・インコーポレイテッドQualcomm Incorporated

Inventor： SEYFOLLAH BAZARJANI ,  MIAO GUOQING ,  JOSEPH R FITZGERALD ,  PRAJAKT V KULKARNI ,  JUSTIN JOSEPH ROSEN GAGNE ,  JEAN H MCALLISTER ,  JEFFREY HINRICHS ,  VAN DER WAGT JAN PAUL

IPC: H03F1/02 ,  H03F3/21 ,  H03F3/22

CPC classification number: H03F1/0222 ,  H03F1/0211 ,  H03F2200/03 ,  H03G3/30 ,  H03G3/3005 ,  H03G3/32

Abstract: PROBLEM TO BE SOLVED: To provide a system and method of improving the efficiency in the power consumption of an audio system.SOLUTION: Power delivered from a power supply analog section 212 to an analog section including a power amplifier 206-L is adjusted in response to a volume level indicated by a volume control module 216 and/or in response to a detected characteristic of an input audio signal. Thus, in this system and method, the analog section is operated in a manner that is related to the level of the signal it is processing. Additionally, the system and method also relate to a technique of adjusting the dynamic ranges of the digital signal and the analog signal to improve the overall dynamic range of the system without needing to consume additional power.

Abstract translation: 要解决的问题：提供一种提高音频系统的功率消耗效率的系统和方法。 解决方案：响应于由音量控制模块216指示的音量水平和/或响应于检测到的特性，调节从电源模拟部分212传递到包括功率放大器206-L的模拟部分的功率 输入音频信号。 因此，在该系统和方法中，模拟部分以与正在处理的信号的电平相关的方式操作。 此外，该系统和方法还涉及调整数字信号和模拟信号的动态范围的技术，以改善系统的整体动态范围，而不需要消耗附加功率。 版权所有（C）2012，JPO＆INPIT

公开(公告)号：HK1049932B

公开(公告)日：2008-06-06

申请号：HK03102105

申请日：2003-03-24

Applicant: QUALCOMM INC

Inventor： TAO CHEN ,  SEYFOLLAH BAZARJANI ,  EDWARD G TIEDEMANN JR

IPC: H04J1/02 ,  H04Q7/22

公开(公告)号：HK1070146A1

公开(公告)日：2005-06-10

申请号：HK05102656

申请日：2005-03-30

Applicant: QUALCOMM INC

Inventor： SEYFOLLAH BAZARJANI ,  JEREMY GOLDBLATT

IPC: G05F20060101 ,  G05F3/26 ,  G05F3/20 ,  H03F20060101 ,  H03F3/45

Abstract: A bias circuit is described for use in biasing an operational amplifier to maintain a constant transconductance divided by load capacitance (i.e. a constant gm/CL) despite temperature and process variations and despite body effects. In one example, the bias circuit includes a pair of current source devices and a switched capacitor (SC) equivalent resistor circuit for developing an equivalent resistance between the current source devices. The equivalent resistor circuit includes a sampling capacitor. First and second clock inputs are connected to the capacitor providing non-overlapping clock signals at a predetermined sampling frequency to establish a resistance equivalent. By providing an SC equivalent resistor circuit clocked by non-overlapping fixed clock signals, the gm/CL of the bias circuit is maintained substantially constant. Hence, a fixed bandwidth is maintained within the operational amplifier being biased. When employed in connection with operational amplifiers of an SC circuit, the constant bandwidth enables the SC circuit to operate at a constant switching speed despite temp and process variations. Furthermore, by positioning the resistance equivalent circuit between the current source devices of the bias circuit, voltage differentials between the sources are eliminated thereby removing any threshold voltage mismatch and thus compensating for body effect variations. Other bias circuit examples are also described including a stray insensitive bias circuit and a bias circuit employing three mutually non-overlapping clock signals.

公开(公告)号：MXPA03006810A

公开(公告)日：2004-05-05

申请号：MXPA03006810

申请日：2002-01-30

Applicant: QUALCOMM INC

Inventor： SEYFOLLAH BAZARJANI

IPC: H03M3/02

Abstract: Un circuito de multi-etapas que incluye un numero de etapas, con por lo menos una etapa siendo de un primer tipo y por lo menos una etapa siendo de un segundo tipo. Cada etapa recibe ya sea una senal de entrada de circuito o una senal de salida de una etapa precedente, procesa, (por ejemplo, filtra) la senal recibida, y proporciona una senal de salida respectiva. Cada primer tipo (o segundo tipo de etapa opera basandose en una o mas senales de reloj que tienen una frecuencia de f, (o fS/N) donde fS es la frecuencia de muestreo y N es un numero entero mayor que uno. Cada etapa de primer tipo puede implementarse con un circuito de doble muestreo correlacionado, un circuito de auto-anulacion, o un circuito pulsador de estabilizacion. Cada etapa de segundo tipo puede implementarse con un circuito de multi-muestreo (es decir, doble muestreo, o muestreo de orden mas alto). El circuito de multi-etapas puede disenarse para implementar un filtro de paso bajo, un ?S ADC o algun otro circuito.