公开(公告)号：ES2543812T3

公开(公告)日：2015-08-24

申请号：ES12716132

申请日：2012-03-14

Applicant: QUALCOMM INC

Inventor： SRIVASTAVA ANKIT ,  WORLEY EUGENE R ,  MIAO GUOQING ,  QUAN XIAOHONG

IPC: H03F1/52 ,  H01L27/02 ,  H02M1/32 ,  H02M3/07

Abstract: Un aparato que comprende: una pluralidad de conmutadores (M1-M6) configurados para sucesivamente acoplar y desacoplar eléctricamente los primer (C1p) y segundo (C1n) nodos de un condensador flotante (125) a una pluralidad de nodos (Vin, Vpos, Vneg, GND), en el que la pluralidad de conmutadores comprende un primer conmutador (M5) que acopla el segundo nodo del condensador flotante a un nodo de tensión de salida negativa (Vneg), el primer conmutador está configurado para acoplar eléctricamente el segundo nodo del condensador flotante al nodo de tensión de salida negativa en respuesta a la detección de un evento de ESD entre un nodo de tensión de suministro (Vdd) y el nodo de tensión de salida negativa.

公开(公告)号：BR112023013647A2

公开(公告)日：2023-12-05

申请号：BR112023013647

申请日：2022-01-05

Applicant: QUALCOMM INC

Inventor： SRIVASTAVA ANKIT ,  WADHWA SAMEER ,  SEYED ARASH MIRHAJ ,  CHEN XIAONAN ,  WANG ZHONGZE

IPC: G11C11/419 ,  G11C7/10 ,  G11C19/28

Abstract: célula de bits de computação em memória com operação de gravação capacitivamente acoplada. é fornecida uma célula de bits de computação em memória que inclui um par de inversores de acoplamento cruzado para armazenar um bit armazenado. a célula de bits de computação em memória inclui uma porta lógica para multiplicar o bit armazenado com um bit de vetor de entrada. um nó de saída para a porta lógica se conecta a uma segunda placa de um capacitor. uma primeira placa do capacitor se conecta a uma linha de leitura de bit. um driver de gravação controla uma tensão de fonte de alimentação para os inversores de acoplamento cruzado, o primeiro comutador, e o segundo comutador para gravar capacitivamente o bit armazenado no par de inversores de acoplamento cruzado.

公开(公告)号：BR112013023580A2

公开(公告)日：2016-12-06

申请号：BR112013023580

申请日：2012-03-14

Applicant: QUALCOMM INC

Inventor： SRIVASTAVA ANKIT ,  WORLEY EUGENE R ,  MIAO GUOQING ,  QUAN XIAOJONG

IPC: H01L27/02 ,  H02M3/07 ,  H03F1/52

公开(公告)号：WO2012115880A8

公开(公告)日：2013-08-29

申请号：PCT/US2012025695

申请日：2012-02-17

Applicant: QUALCOMM INC ,  QUAN XIAOHONG ,  SRIVASTAVA ANKIT

Inventor： QUAN XIAOHONG ,  SRIVASTAVA ANKIT

IPC: H03K5/13

CPC classification number: H03K5/133 ,  H03L7/16

Abstract: An integrated circuit for delaying a clock signal using a delay cell is described. The integrated circuit includes a current starved inverter. The current starved inverter includes a switched capacitor current source with a first dummy inverter, a first amplifier coupled to the first dummy inverter and a first capacitor coupled to the first amplifier via a first switch. The current starved inverter also includes a first transistor coupled to the current source. The integrated circuit also includes a second capacitor. A delay applied to the clock signal is dependent on a ratio between the first capacitor and the second capacitor. The first capacitor and the second capacitor may be located in proximity such that process, voltage and temperature variations affect the first capacitor and the second capacitor similarly and the delay applied to the clock signal is independent of process, voltage and temperature variations

Abstract translation: 描述了使用延迟单元来延迟时钟信号的集成电路。 集成电路包括电流欠压逆变器。 目前的饥饿逆变器包括具有第一虚拟逆变器的开关电容器电流源，耦合到第一虚拟反相器的第一放大器和经由第一开关耦合到第一放大器的第一电容器。 目前的饥饿逆变器还包括耦合到电流源的第一晶体管。 集成电路还包括第二电容器。 施加到时钟信号的延迟取决于第一电容器和第二电容器之间的比率。 第一电容器和第二电容器可以位于接近处，使得过程，电压和温度变化类似地影响第一电容器和第二电容器，并且施加到时钟信号的延迟与过程，电压和温度变化无关

公开(公告)号：WO2012103475A3

公开(公告)日：2012-11-01

申请号：PCT/US2012022965

申请日：2012-01-27

Applicant: QUALCOMM INC ,  SRIVASTAVA ANKIT ,  HUANG XUHAO ,  QUAN XIAOHONG

Inventor： SRIVASTAVA ANKIT ,  HUANG XUHAO ,  QUAN XIAOHONG

IPC: H03K19/0185

CPC classification number: G06F13/4072 ,  H03K19/018528

Abstract: A high voltage tolerant differential receiver circuit includes a voltage divider ladder that is operative to divide in half differential input signals that are greater than threshold voltages of the voltage divider ladder. A pass gate circuit is operative to receive differential input signals that are below the threshold voltage of the voltage divider ladder. Outputs from the voltage divider ladder and the pass gate circuit are provided to separate comparators. Output from the comparators are combined to generate a signal in the voltage domain of receiver circuitry.

Abstract translation: 高耐压差分接收器电路包括分压器梯形图，其可操作地分压大于分压器梯形图的阈值电压的半差分输入信号。 通路电路用于接收低于分压器梯形图的阈值电压的差分输入信号。 来自分压器梯形图和通过门电路的输出提供给单独的比较器。 来自比较器的输出被组合以在接收器电路的电压域中产生信号。

公开(公告)号：WO2013149226A2

公开(公告)日：2013-10-03

申请号：PCT/US2013034739

申请日：2013-03-30

Applicant: QUALCOMM INC

Inventor： SRIVASTAVA ANKIT ,  DHANASEKARAN VIJAYAKUMAR

IPC: H02M3/158

CPC classification number: H02M3/156 ,  H02M1/12 ,  H02M2001/0025 ,  H02M2001/0032 ,  Y02B70/16

Abstract: Disclosed are systems and methods for suppressing voltage peaking in a buck regulator. In one aspect, a buck regulator comprises: a pulse-width modulator (PWM) that generates a pulsed signal; a switch operable to selectively connect the regulator to a DC power supply in response to the pulsed signal and output a pulsed output DC signal; a filter for filtering out high frequency noise from the pulsed output DC signal and generating a regulated output signal; an integrator for comparing the pulsed output DC signal with a reference voltage signal and generating an error signal for input to the PWM; a subtractor operable to subtract the reference voltage signal from the filtered output signal to generate an error feedback signal; and an adder operable to add the error feedback signal to the error signal for input to the pulse-width modulator in order to suppress voltage peaks in the filtered output signal.

Abstract translation: 公开了用于抑制降压调节器中的峰值电压的系统和方法。 一方面，降压调节器包括：产生脉冲信号的脉冲宽度调制器（PWM）; 开关，其可操作以响应于所述脉冲信号选择性地将调节器连接到DC电源并输出脉冲输出DC信号; 用于从脉冲输出DC信号滤除高频噪声并产生调节输出信号的滤波器; 用于将脉冲输出DC信号与参考电压信号进行比较并产生用于输入到PWM的误差信号的积分器; 减法器，用于从滤波的输出信号中减去参考电压信号以产生误差反馈信号; 以及加法器，用于将误差反馈信号添加到误差信号以输入到脉宽调制器，以便抑制经滤波的输出信号中的电压峰值。

公开(公告)号：WO2012009586A3

公开(公告)日：2012-05-18

申请号：PCT/US2011044091

申请日：2011-07-15

Applicant: QUALCOMM INC ,  SRIVASTAVA ANKIT ,  QUAN XIAOHONG

Inventor： SRIVASTAVA ANKIT ,  QUAN XIAOHONG

IPC: H03G3/34 ,  H03K5/24

CPC classification number: H04B1/1027 ,  H03G3/341 ,  H03K5/2481

Abstract: A squelch detection circuit and method involves a first comparator (540) coupled to a complimentary input signal pair (inp, inn) and having a first polarity output. A second comparator (550) coupled to the complimentary input signal pair has a second polarity output. An offset associated with complimentary input signal pair establishes a positive squelch threshold and a negative squelch threshold. A calibration unit (560) coupled to the first comparator and the second comparator generates a digital output including threshold settings and calibration settings to the first comparator and to the second comparator. The digital output can be associated with establishing the offset and with calibrating the positive squelch threshold and the negative squelch threshold.

Abstract translation: 静噪检测电路和方法涉及耦合到互补输入信号对（inp，inn）并且具有第一极性输出的第一比较器（540）。 耦合到互补输入信号对的第二比较器（550）具有第二极性输出。 与补偿输入信号对相关的偏移量建立正静噪阈值和负静噪阈值。 耦合到第一比较器和第二比较器的校准单元（560）产生包括阈值设置和校准设置的数字输出到第一比较器和第二比较器。 数字输出可以与建立偏移量相关联，并校准正静噪阈值和负静噪阈值。

公开(公告)号：WO2016003597A2

公开(公告)日：2016-01-07

申请号：PCT/US2015034295

申请日：2015-06-04

Applicant: QUALCOMM INC

Inventor： LU JINGXUE ,  SRIVASTAVA ANKIT ,  SIENKO MATTHEW DAVID ,  MISHRA MANU ,  ZHANG SHENG

IPC: H03F3/217

CPC classification number: H03F1/32 ,  H03F1/3205 ,  H03F3/185 ,  H03F3/217 ,  H03F3/2171 ,  H03F3/2173 ,  H03F3/45475 ,  H03F2200/03 ,  H03F2200/351 ,  H03F2203/45512 ,  H03F2203/45528

Abstract: A switching amplifier includes a compensation circuit to compensate for DC offset in the amplifier, to enhance operation of the switching amplifier. The compensation circuit may comprise a SAR ADC, where the DAC element can be used to provide a compensation voltage. The switching amplifier may further include a PWM modulator configured to avoid cross-talk to further enhance operation of the switching amplifier.

Abstract translation: 开关放大器包括补偿电路以补偿放大器中的DC偏移，以增强开关放大器的操作。 补偿电路可以包括SAR ADC，其中DAC元件可以用于提供补偿电压。 开关放大器还可以包括PWM调制器，该PWM调制器被配置为避免串扰以进一步增强开关放大器的操作。

公开(公告)号：WO2012125766A2

公开(公告)日：2012-09-20

申请号：PCT/US2012029128

申请日：2012-03-14

Applicant: QUALCOMM INC ,  QUAN XIAOHONG ,  SRIVASTAVA ANKIT ,  MIAO GUOQING

Inventor： QUAN XIAOHONG ,  SRIVASTAVA ANKIT ,  MIAO GUOQING

CPC classification number: H02M3/07 ,  H02M1/36 ,  H02M2001/0045 ,  H02M2003/071 ,  H02M2003/072

Abstract: Techniques for reducing surge current in charge pumps. In an exemplary embodiment, one or more switches coupling a terminal of a flying capacitor to a voltage supply are configured to have variable on-resistance. When the charge pump is configured to switch a gain mode from a lower gain to a higher gain, the one or more variable resistance switches are configured to have a decreasing resistance profile over time. In this manner, surge current drawn from the voltage supply at the outset of the gain switch may be limited, while the on-resistance during steady-state charging and discharging may be kept low. Similar techniques are provided to decrease the surge current from a bypass switch coupling the supply voltage to a positive output voltage of the charge pump.

Abstract translation: 降低电荷泵浪涌电流的技术。 在示例性实施例中，将飞跨电容器的端子耦合到电压源的一个或多个开关被配置为具有可变的导通电阻。 当电荷泵被配置为将增益模式从较低增益切换到较高增益时，一个或多个可变电阻开关被配置为具有随时间减小的电阻分布。 以这种方式，可以限制在增益开关开始时从电压源引出的浪涌电流，而稳态充放电期间的导通电阻可以保持较低。 提供了类似的技术以减少将电源电压耦合到电荷泵的正输出电压的旁路开关的浪涌电流。