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    Transmitter architectures for communications systems
    1.
    发明专利
    Transmitter architectures for communications systems 有权
    用于通信系统的发射机结构

    公开(公告)号：JP2012016026A

    公开(公告)日：2012-01-19

    申请号：JP2011168761

    申请日：2011-08-01

    Applicant: Qualcomm Inc ,  クゥアルコム・インコーポレイテッドQualcomm Incorporated

    Inventor： SAAD YOUNIS ,  EMILIA SCHMICK ,  THOMAS WILBORN ,  HAITAO ZANG ,  FILIPOVIC DANIEL ,  KAUFMANN RALF ,  JIAN LIN

    IPC: H03F1/02 ,  H04B1/04 ,  H03F3/24 ,  H03G3/20 ,  H03G3/30 ,  H04B7/005 ,  H04B7/24

    CPC classification number: H03G3/3042 ,  H03F2203/7239 ,  H03G1/0088

    Abstract: PROBLEM TO BE SOLVED: To provide a method for controlling a transient current at an output power of a transmitter performing signal transmission.SOLUTION: The transmitter includes a first element having a first time response and a second element having a second time response, in which the first time response is faster than the second time response. The method comprises: receiving a first command to adjust a gain of the first element; receiving a second command to adjust a gain of the second element; delaying the first command by a particular time period; adjusting the gain of the second gain element in accordance with the second command; and adjusting the gain of the first gain element in accordance with the delayed first command.

    Abstract translation: 要解决的问题：提供一种用于控制在执行信号传输的发射机的输出功率下的瞬态电流的方法。 解决方案：发射机包括具有第一时间响应的第一元件和具有第二时间响应的第二元件，其中第一时间响应比第二时间响应快。 该方法包括：接收第一命令以调整第一元素的增益; 接收第二命令以调整所述第二元件的增益; 在特定时间段内延迟第一个命令; 根据第二指令调整第二增益元件的增益; 以及根据延迟的第一命令调整第一增益元件的增益。 版权所有（C）2012，JPO＆INPIT

    Transmitter architectures for communications systems
    2.
    发明专利
    Transmitter architectures for communications systems 有权
    用于通信系统的发射机结构

    公开(公告)号：JP2012016025A

    公开(公告)日：2012-01-19

    申请号：JP2011168760

    申请日：2011-08-01

    Applicant: Qualcomm Inc ,  クゥアルコム・インコーポレイテッドQualcomm Incorporated

    Inventor： SAAD YOUNIS ,  EMILIA SCHMICK ,  THOMAS WILBORN ,  HAITAO ZANG ,  FILIPOVIC DANIEL ,  KAUFMANN RALF ,  JIAN LIN

    IPC: H03G3/20 ,  H04B1/04 ,  H03G3/30 ,  H04B7/005 ,  H04B7/24

    CPC classification number: H03G3/3042 ,  H03F2203/7239 ,  H03G1/0088

    Abstract: PROBLEM TO BE SOLVED: To provide a transmitter architecture for a communications system of high performance, which consumes less electric power and which requires low cost.SOLUTION: There is provided a method for adjusting signal gain in a transmitter having a first gain element and a second gain element, in which the first gain element responds to an asynchronous first update clock and the second gain element responds to an asynchronous second update clock. The method comprises: receiving determinations for first and second gain transmission characteristics and a first gain setting value for the first gain element and a second gain setting value for the second gain element; adjusting the second gain setting value with a particular gain offset value based on the first gain setting value; determining a linearized gain setting value corresponding to the adjusted second gain setting value; adjusting a gain of the first gain element with the first gain setting value; and adjusting a gain of the second gain setting value with the linearized gain setting value.

    Abstract translation: 要解决的问题：提供一种高性能通信系统的发射机架构，其消耗较少的电力并且需要低成本。 解决方案：提供了一种用于调整具有第一增益元件和第二增益元件的发射器中的信号增益的方法，其中第一增益元件响应异步第一更新时钟，第二增益元件响应异步 第二更新时钟。 该方法包括：接收第一增益传输特性的确定和第一增益元件的第一增益设置值和第二增益元件的第二增益设置值; 基于所述第一增益设定值，以特定增益偏移值调整所述第二增益设定值; 确定与所述调整后的第二增益设定值对应的线性化增益设定值; 用第一增益设定值调节第一增益元件的增益; 以及利用所述线性化增益设定值来调整所述第二增益设定值的增益。 版权所有（C）2012，JPO＆INPIT

    Digital-to-analog interface circuit having adjustable time response
    3.
    发明专利
    Digital-to-analog interface circuit having adjustable time response 审中-公开
    具有可调节时间响应的数字到模拟接口电路

    公开(公告)号：JP2012075130A

    公开(公告)日：2012-04-12

    申请号：JP2011237247

    申请日：2011-10-28

    Applicant: Qualcomm Inc ,  クゥアルコム・インコーポレイテッドQualcomm Incorporated

    Inventor： YOUNIS SAED ,  EMILIA SCHMICK ,  THOMAS WILBORN

    IPC: H03M3/02 ,  H03M7/32 ,  H03F3/24 ,  H03G3/20 ,  H03G3/30 ,  H03M3/00

    CPC classification number: H03F3/24 ,  H03F2200/331 ,  H03G3/3036 ,  H03M3/374 ,  H03M3/50 ,  H03M7/3031

    Abstract: PROBLEM TO BE SOLVED: To provide an interface circuit having adjustable time response while maintaining small ripple amplitude.SOLUTION: An interface circuit 310 for converting a digital signal to an analog signal includes a time response adjustment circuit 312, a modulator 314 and a filter 316. The time response adjustment circuit 312 receives the digital signal and generates an adjusted signal. The modulator 314 couples to the time response adjustment circuit 312, receives the adjusted signal, and generates a modulator signal. The filter 316 couples to the modulator, receives the modulator signal, and generates the analog signal.

    Abstract translation: 要解决的问题：提供具有可调整的时间响应的接口电路，同时保持小的纹波幅度。 解决方案：用于将数字信号转换为模拟信号的接口电路310包括时间响应调整电路312，调制器314和滤波器316.时间响应调整电路312接收数字信号并产生经调整的信号。 调制器314耦合到时间响应调整电路312，接收经调整的信号，并产生调制器信号。 滤波器316耦合到调制器，接收调制器信号，并产生模拟信号。 版权所有（C）2012，JPO＆INPIT

    Architecture of transmitter for communication system
    5.
    发明专利
    Architecture of transmitter for communication system 有权
    发射机通信系统架构

    公开(公告)号：JP2012010366A

    公开(公告)日：2012-01-12

    申请号：JP2011168763

    申请日：2011-08-01

    Applicant: Qualcomm Inc ,  クゥアルコム・インコーポレイテッドQualcomm Incorporated

    Inventor： SAAD YOUNIS ,  EMILIA SCHMICK ,  THOMAS WILBORN ,  HAITAO ZANG ,  FILIPOVIC DANIEL ,  KAUFMANN RALF ,  JIAN LIN

    IPC: H03G3/20 ,  H04B1/04 ,  H03F1/02 ,  H03F1/32 ,  H03F3/24 ,  H03G3/30 ,  H04B7/005 ,  H04B7/24

    CPC classification number: H03G3/3042 ,  H03F2203/7239 ,  H03G1/0088

    Abstract: PROBLEM TO BE SOLVED: To provide a controller circuit for accelerating response time, improving linearity in adjustment of output power, reducing interference, reducing power consumption, lowering circuit complexity and lowering costs by controlling the operation of a transmitter of a communication system.SOLUTION: A variable gain element has a variable gain covering a particular gain range. A power amplifier section is connected to the variable gain element and includes many discrete gain settings, and one of the gain settings is a bypass setting. The controller circuit supplies control signals for the variable gain element and the power amplifier section. The gains of the variable gain element and the power amplifier section are updated so as to reduce transients in output transmission power and to perform linear adjustment of an output transmission power level. The variable gain element and the power amplifier section are controlled to reduce the power consumption by turning off the power of the power amplifier section when not needed for instance.

    Abstract translation: 要解决的问题：为了提供控制电路，通过控制通信系统的发射机的操作来提高响应时间，提高调节输出功率的线性度，减少干扰，降低功耗，降低电路复杂度并降低成本 。

    解决方案：可变增益元件具有覆盖特定增益范围的可变增益。 功率放大器部分连接到可变增益元件，并包括许多离散增益设置，其中一个增益设置是旁路设置。 控制器电路为可变增益元件和功率放大器部分提供控制信号。 更新可变增益元件和功率放大器部分的增益，以便减少输出发射功率的瞬变并且执行输出发射功率电平的线性调节。 控制可变增益元件和功率放大器部分，以便在不需要时关闭功率放大器部分的功率来降低功耗。 版权所有（C）2012，JPO＆INPIT

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    7.
    发明专利
    "TANSMITTER ARCHITECTURES FOR COMMUNICATIONS SYSTEMS" 未知

    公开(公告)号：MY127914A

    公开(公告)日：2006-12-29

    申请号：MYPI20010962

    申请日：2001-03-02

    Applicant: QUALCOMM INC

    Inventor： SAED YOUNIS ,  THOMAS WILBORN ,  DANIEL FILIPOVIC ,  JIAN LIN ,  EMILIJA SIMIC ,  HAITAO ZHANG ,  RALPH KAUFMAN

    IPC: H04B1/04 ,  H03G3/20 ,  H04L27/04 ,  H03G3/30 ,  H04B7/005 ,  H04B7/24

    Abstract: TRANSMITTER ARCHITECTURES FOR A COMMUNICATIONS SYSTEM HAVING IMPROVED PERFORMANCE OVER CONVENTIONAL TRANSMITTER ARCHITECTURES.THE IMPROVEMENTS INCLUDE A COMBINATION OF THE FOLLOWING: FASTER RESPONSE TIME FOR THE CONTROL SIGNALS (PA_ON, PA_R, PA_RI, PA_RU, VGA_GAIN, TX_AGC, OS_GAIN), IMPROVED LINEARITY, REDUCED INTERFERENCE, REDUCED POWER CONSUMPTION, LOWER CIRCUIT COMPLEXITY, AND LOWER COSTS. FOR A CELLULAR APPLICATION, THESE IMPROVEMENTS CAN LEAD TO INCREASED SYSTEM CAPACITY, SMALLER TELEPHONE SIZE, INCREASED TALK AND STANDBY TIMES, AND GREATER ACCEPTANCE OF THE PRODUCT. CIRCUITRY IS PROVIDED TO SPEED UP THE RESPONSE TIME OF A CONTROL SIGNAL. THE CONTROL LOOP FOR VARIOUS ELEMENTS IN THE TRANSMIT SIGNAL PATH ARE INTEGRATED. A GAIN CONTROL MECHANISM ALLOWS FOR ACCURATE ADJUSTMENT OF THE OUTPUT TRANSMIT POWER LEVEL. CONTROL MECHANISMS ARE PROVIDED TO POWER DOWN THE POWER AMPLIFIER (128, 840), OR THE ENTIRE TRANSMIT SIGNAL PATH, WHEN NOT NEEDED. THE GAINS OF THE VARIOUS ELEMENTS IN THE TRANSMIT SIGNAL PATH ARE CONTROLLED TO REDUCE TRANSIENTS IN THE OUTPUT TRANSMIT POWER, AND TO ALSO ENSURE THAT TRANSIENTS ARE DOWNWARD.(FIG 1)

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