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1.发明申请
公开(公告)号：WO2003065574A2
公开(公告)日：2003-08-07
申请号：PCT/US2003/002913
申请日：2003-01-31
Applicant: QUALCOMM INCORPORATED
Inventor： BARNETT, Kenneth
IPC: H03G
CPC classification number: H03G3/3042 , H03H11/30
Abstract: A variable impedance load (104) is provided at the output of a radio frequency (RF) driver amplifier (102) having a variable gain. In an exemplary embodiment, the variable load (104) comprises a resistor (R) in series with a semiconductor device (M 1 ). The semiconductor device (M 1 ) has an impedance level determined by a drive current. The value of the drive current is related to the gain of the RF driver amplifier (102).
Abstract translation: 可变阻抗负载104设置在具有可变增益的射频RF驱动器放大器102的输出端。 在示例性实施例中，可变负载104包括与半导体器件M1串联的电阻器R. 半导体器件M1具有由驱动电流确定的阻抗水平。 驱动电流的值与RF驱动放大器102的增益有关。
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公开(公告)号：WO2010033855A3
公开(公告)日：2010-03-25
申请号：PCT/US2009/057555
申请日：2009-09-18
Applicant: QUALCOMM Incorporated , ZHANG, Kun , BARNETT, Kenneth
Inventor： ZHANG, Kun , BARNETT, Kenneth
Abstract: A latch includes three circuits. The first circuit drives a first output (QB) to a first level when a first input (D) and a first clock phase (CK) are both low, to a second level when D and CK are both high, and provides high impedance (HI-Z) when different logic levels are applied to D and CK. The second circuit drives a second output (Q) to the first level when a third input (DB) and a complimentary clock phase (CKB) are both low, to the second level when DB and CKB are both high, and provides HI-Z when different logic levels are applied to DB and CKB. The third circuit maintains voltages of Q and QB when the first and second circuits provide HI-Z at Q and QB. Odd-number dividers constructed with such latches produce 50% duty cycle operation without restricting output pulse widths to integer multiples of input periods.
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Patent Agency Ranking3.发明申请CONTINUOUSLY VARIABLE GAIN RADIO FREQUENCY DRIVER AMPLIFIER HAVING LINEAR IN DECIBEL GAIN CONTROL CHARACTERISTICS 审中-公开具有线性差分增益控制特性的连续可变增益射频驱动放大器
公开(公告)号：WO2004045226A2
公开(公告)日：2004-05-27
申请号：PCT/US2003/036231
申请日：2003-11-12
Applicant: QUALCOMM INCORPORATED
Inventor： BARNETT, Kenneth , WALKER, Brett C. , GARD, Kevin
IPC: H04Q7/00
CPC classification number: H04B5/00 , H03F1/301 , H03G1/04 , H03G3/3036 , H03G3/3042 , H03G7/001
Abstract: A radio frequency (RF) driver amplifier system and method that provides linear in decibel gain control is provided. The RF driver amplifier system comprises a linear transconductor receiving an input voltage and providing a controlled current based on input voltage received, temperature compensation circuitry for varying current from the linear transconductor according to absolute temperature, an exponential current controller receiving current varied according to temperature and providing an exponential current in response, and an inductive degeneration compensator receiving exponential current and providing a control current to driver amplifier circuitry , thereby compensating for inductive degeneration due to at least one inductor in the driver amplifier circuitry . Control current passes from the inductive degeneration compensator to the driver amplifier circuitry . Output gain from the driver amplifier circuitry varies linearly in decibels with respect to the input voltage.
Abstract translation: 提供了一种提供线性分贝增益控制的射频（RF）驱动放大器系统和方法。 该RF驱动放大器系统包括接收输入电压并基于接收到的输入电压提供受控电流的线性跨导器，用于根据绝对温度改变来自线性跨导器的电流的温度补偿电路，接收根据温度变化的电流的指数电流控制器和 提供响应的指数电流，以及接收指数电流并向驱动器放大器电路提供控制电流从而补偿由于驱动器放大器电路中的至少一个电感器引起的电感负反馈的电感负反馈补偿器。 控制电流从感性负反馈补偿器传递到驱动器放大器电路。 来自驱动器放大器电路的输出增益相对于输入电压以分贝线性变化。
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公开(公告)号：WO2003065574A3
公开(公告)日：2003-08-07
申请号：PCT/US2003/002913
申请日：2003-01-31
Applicant: QUALCOMM INCORPORATED
Inventor： BARNETT, Kenneth
IPC: H03F1/56
Abstract: A variable impedance load (104) is provided at the output of a radio frequency (RF) driver amplifier (102) having a variable gain. In an exemplary embodiment, the variable load (104) comprises a resistor (R) in series with a semiconductor device (M 1 ). The semiconductor device (M 1 ) has an impedance level determined by a drive current. The value of the drive current is related to the gain of the RF driver amplifier (102).
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5.发明公开
公开(公告)号：EP1568236A2
公开(公告)日：2005-08-31
申请号：EP03783406.6
申请日：2003-11-12
Applicant: QUALCOMM INCORPORATED
Inventor： BARNETT, Kenneth , WALKER, Brett C. , GARD, Kevin
IPC: H04Q7/00
CPC classification number: H04B5/00 , H03F1/301 , H03G1/04 , H03G3/3036 , H03G3/3042 , H03G7/001
Abstract: A radio frequency (RF) driver amplifier system and method that provides linear in decibel gain control is provided. The RF driver amplifier system comprises a linear transconductor receiving an input voltage and providing a controlled current based on input voltage received, temperature compensation circuitry for varying current from the linear transconductor according to absolute temperature, an exponential current controller receiving current varied according to temperature and providing an exponential current in response, and an inductive degeneration compensator receiving exponential current and providing a control current to driver amplifier circuitry , thereby compensating for inductive degeneration due to at least one inductor in the driver amplifier circuitry . Control current passes from the inductive degeneration compensator to the driver amplifier circuitry . Output gain from the driver amplifier circuitry varies linearly in decibels with respect to the input voltage.
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公开(公告)号：EP2342823A2
公开(公告)日：2011-07-13
申请号：EP09792735.4
申请日：2009-09-18
Applicant: QUALCOMM Incorporated
Inventor： ZHANG, Kun , BARNETT, Kenneth
IPC: H03K3/356
CPC classification number: H03K3/356121 , H03K5/1565 , H03K23/544
Abstract: A latch includes three circuits. The first circuit drives a first output (QB) to a first level when a first input (D) and a first clock phase (CK) are both low, to a second level when D and CK are both high, and provides high impedance (HI-Z) when different logic levels are applied to D and CK. The second circuit drives a second output (Q) to the first level when a third input (DB) and a complimentary clock phase (CKB) are both low, to the second level when DB and CKB are both high, and provides HI-Z when different logic levels are applied to DB and CKB. The third circuit maintains voltages of Q and QB when the first and second circuits provide HI-Z at Q and QB. Odd-number dividers constructed with such latches produce 50% duty cycle operation without restricting output pulse widths to integer multiples of input periods.
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7.发明授权
公开(公告)号：EP1568236B1
公开(公告)日：2009-12-23
申请号：EP03783406.6
申请日：2003-11-12
Applicant: QUALCOMM INCORPORATED
CPC classification number: H04B5/00 , H03F1/301 , H03G1/04 , H03G3/3036 , H03G3/3042 , H03G7/001
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