公开(公告)号：WO2017204902A1

公开(公告)日：2017-11-30

申请号：PCT/US2017/025547

申请日：2017-03-31

Applicant: QUALCOMM INCORPORATED

Inventor： ZANUSO, Marco ,  ELBADRY, Mohammad ,  HUNG, Tsai-Pi ,  SRIDHARA, Ravi ,  GATTA, Francesco ,  ZHUANG, Jingcheng

IPC: H03L7/14

CPC classification number: H04L7/033 ,  H03L7/14 ,  H03L7/143 ,  H03L7/1976 ,  H03L2207/08 ,  H04L5/14 ,  H04L69/28 ,  H04W84/042

Abstract: A phase discontinuity mitigation implementation within a phased lock loop (PLL) improves throughput of a radio access technology. The throughput is improved by maintaining a phase of the PLL while powering off some devices of the PLL, such as a local oscillator (LO) frequency divider. In one instance, when the PLL is powered down, one or more portions of a delta sigma modulator for the PLL are clocked with a reference clock for the PLL. This implementation maintains phase continuity when the first phase lock loop turns back on.

Abstract translation: 相位锁定环（PLL）内的相位不连续性缓解实现提高了无线电接入技术的吞吐量。 在断开PLL的一些器件（如本地振荡器（LO）分频器）时，通过保持PLL的相位来改善吞吐量。 在一个实例中，当PLL断电时，PLL的一个或多个部分的Δ-Σ调制器以PLL的参考时钟为时钟。 当第一个锁相环打开时，此实现可保持相位连续性。