公开(公告)号：WO2017058417A1

公开(公告)日：2017-04-06

申请号：PCT/US2016/048771

申请日：2016-08-25

Applicant: QUALCOMM INCORPORATED

Inventor： JOSE, Edwin ,  DROP, Michael

IPC: G11C11/406 ,  G06F13/16

CPC classification number: G11C11/40615 ,  G06F13/1636 ,  G11C11/40611 ,  G11C11/40626 ,  G11C11/4076 ,  G11C11/4087 ,  G11C2211/4067

Abstract: A memory controller is configured to communicate to a DRAM an indication of when a most-recent memory-controller-triggered refresh cycle occurred prior to a transition to a self-refresh mode of operation in which the DRAM self-triggers its refresh cycles.

Abstract translation: 存储器控制器被配置为向DRAM通信指示何时最近存储器 - 控制器触发的刷新周期在转换到其中自动触发其刷新周期的自刷新操作模式之前发生。

公开(公告)号：WO2017023408A1

公开(公告)日：2017-02-09

申请号：PCT/US2016/035520

申请日：2016-06-02

Applicant: QUALCOMM INCORPORATED

Inventor： JOSE, Edwin ,  WANG, Tao

IPC: G06F13/16

CPC classification number: G06F11/1471 ,  G06F3/0619 ,  G06F3/0632 ,  G06F3/0679 ,  G06F13/1668 ,  G06F2201/805 ,  G06F2201/84 ,  G06F2201/85

Abstract: Some aspects of the disclosure include a self-refresh entry sequence for a memory, such as a DRAM, that may be used to avoid a frequency mismatch between a system processor and a system memory. The self-refresh entry sequence may signal the memory to reset the frequency set point state and default to the power-up state upon a self-refresh process exit. In another aspect, a new mode register may be used to indicate that the frequency set point needs to be reset after the next self-refresh entry command. In this aspect, the processor will execute a mode register write command followed by a self-refresh entry in response to the occurrence of a crash event. Then, the memory will reset to the default frequency set point by the end of self-refresh entry execution.

Abstract translation: 本公开的一些方面包括用于诸如DRAM的存储器的自刷新入口序列，其可以用于避免系统处理器和系统存储器之间的频率不匹配。 自刷新入口序列可能会在存储器中发信号通知复位频率设定点状态，并在自刷新过程退出时默认为上电状态。 另一方面，可以使用新的模式寄存器来指示频率设定点需要在下一个自刷新输入命令之后复位。 在这方面，处理器将执行模式寄存器写入命令，随后响应于碰撞事件的发生而进行自刷新条目。 然后，在自刷新输入执行结束时，存储器将重置为默认频率设定点。

公开(公告)号：WO2019027542A1

公开(公告)日：2019-02-07

申请号：PCT/US2018/034454

申请日：2018-05-24

Applicant: QUALCOMM INCORPORATED

Inventor： CHAMARTY, Vinod ,  NGUYEN, Trang ,  JOSE, Edwin ,  KANG, Xin ,  SWEENEY, Sean ,  DROP, Michael ,  ANDREEV, Boris ,  AQUIL, Farrukh

IPC: G06F1/32

Abstract: Micro-idle power in a subsystem of a portable computing device may be actively managed based on client voting. Each client vote may include a client activity status indication and a client latency tolerance indication. Votes are aggregated to provide an aggregate client latency tolerance, which may be used to obtain a set of micro-idle time values. Micro-idle timers in the subsystem may be set to associated micro-idle time values. The micro-idle timers determine whether one or more of the micro-idle time values have elapsed. A power management policy associated with each micro-idle time value determined to have elapsed may be applied to a portion of the subsystem.

公开(公告)号：WO2014189551A1

公开(公告)日：2014-11-27

申请号：PCT/US2014/000141

申请日：2014-06-02

Applicant: QUALCOMM INCORPORATED

Inventor： JOSE, Edwin ,  DROP, Michael ,  HUANG, Xuhao ,  SANKURATRI, Raghu ,  SRIRAMAGIRI, Deepti ,  PEDRALI-NOY, Marzio

IPC: G06F13/16 ,  G11C7/22

CPC classification number: G11C11/4076 ,  G06F13/1689 ,  G11C7/1084 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/4093 ,  G11C2207/2254 ,  H03L7/093 ,  Y02D10/14

Abstract: In one embodiment, a memory interface comprises a cleanup phase-locked loop (PLL) configured to receive a reference clock signal, and to generate a clean clock signal based on the reference clock signal. The memory interface also comprises a synchronization circuit configured to receive data, a data clock signal, and the clean clock signal, wherein the synchronization circuit is further configured to sample the data using the data clock signal, and to synchronize the sampled data with the clean clock signal.

Abstract translation: 在一个实施例中，存储器接口包括被配置为接收参考时钟信号的清理锁相环（PLL），并且基于参考时钟信号产生干净的时钟信号。 存储器接口还包括被配置为接收数据，数据时钟信号和清洁时钟信号的同步电路，其中同步电路还被配置为使用数据时钟信号对数据进行采样，并使采样数据与干净的 时钟信号。

公开(公告)号：EP3304325A1

公开(公告)日：2018-04-11

申请号：EP16729728.2

申请日：2016-06-02

Applicant: Qualcomm Incorporated

Inventor： JOSE, Edwin ,  WANG, Tao

IPC: G06F13/16

CPC classification number: G06F11/1471 ,  G06F3/0619 ,  G06F3/0632 ,  G06F3/0679 ,  G06F13/1668 ,  G06F2201/805 ,  G06F2201/84 ,  G06F2201/85

Abstract: Some aspects of the disclosure include a self-refresh entry sequence for a memory, such as a DRAM, that may be used to avoid a frequency mismatch between a system processor and a system memory. The self-refresh entry sequence may signal the memory to reset the frequency set point state and default to the power-up state upon a self-refresh process exit. In another aspect, a new mode register may be used to indicate that the frequency set point needs to be reset after the next self-refresh entry command. In this aspect, the processor will execute a mode register write command followed by a self-refresh entry in response to the occurrence of a crash event. Then, the memory will reset to the default frequency set point by the end of self-refresh entry execution.

公开(公告)号：EP3357065B1

公开(公告)日：2019-06-26

申请号：EP16759956.2

申请日：2016-08-25

Applicant: Qualcomm Incorporated

Inventor： JOSE, Edwin ,  DROP, Michael

IPC: G11C11/406 ,  G06F13/16

公开(公告)号：EP3304325B1

公开(公告)日：2019-03-20

申请号：EP16729728.2

申请日：2016-06-02

Applicant: Qualcomm Incorporated

Inventor： JOSE, Edwin ,  WANG, Tao

IPC: G06F13/16

公开(公告)号：EP3357065A1

公开(公告)日：2018-08-08

申请号：EP16759956.2

申请日：2016-08-25

Applicant: Qualcomm Incorporated

Inventor： JOSE, Edwin ,  DROP, Michael

IPC: G11C11/406 ,  G06F13/16

CPC classification number: G11C11/40615 ,  G06F13/1636 ,  G11C11/40611 ,  G11C11/40626 ,  G11C11/4076 ,  G11C11/4087 ,  G11C2211/4067

Abstract: A memory controller is configured to communicate to a DRAM an indication of when a most-recent memory-controller-triggered refresh cycle occurred prior to a transition to a self-refresh mode of operation in which the DRAM self-triggers its refresh cycles.

公开(公告)号：EP3028161B1

公开(公告)日：2018-07-18

申请号：EP14748318.4

申请日：2014-06-02

Applicant: Qualcomm Incorporated

Inventor： JOSE, Edwin ,  DROP, Michael ,  HUANG, Xuhao ,  SANKURATRI, Raghu ,  SRIRAMAGIRI, Deepti ,  PEDRALI-NOY, Marzio

IPC: G06F13/16 ,  G11C7/22

CPC classification number: G11C11/4076 ,  G06F13/1689 ,  G11C7/1084 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/4093 ,  G11C2207/2254 ,  H03L7/093 ,  Y02D10/14

Abstract: In one embodiment, a memory interface comprises a cleanup phase-locked loop (PLL) configured to receive a reference clock signal, and to generate a clean clock signal based on the reference clock signal. The memory interface also comprises a synchronization circuit configured to receive data, a data clock signal, and the clean clock signal, wherein the synchronization circuit is further configured to sample the data using the data clock signal, and to synchronize the sampled data with the clean clock signal.

公开(公告)号：EP3028161A1

公开(公告)日：2016-06-08

申请号：EP14748318.4

申请日：2014-06-02

Applicant: Qualcomm Incorporated

Inventor： JOSE, Edwin ,  DROP, Michael ,  HUANG, Xuhao ,  SANKURATRI, Raghu ,  SRIRAMAGIRI, Deepti ,  PEDRALI-NOY, Marzio

IPC: G06F13/16 ,  G11C7/22

CPC classification number: G11C11/4076 ,  G06F13/1689 ,  G11C7/1084 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/4093 ,  G11C2207/2254 ,  H03L7/093 ,  Y02D10/14

Abstract: In one embodiment, a memory interface comprises a cleanup phase-locked loop (PLL) configured to receive a reference clock signal, and to generate a clean clock signal based on the reference clock signal. The memory interface also comprises a synchronization circuit configured to receive data, a data clock signal, and the clean clock signal, wherein the synchronization circuit is further configured to sample the data using the data clock signal, and to synchronize the sampled data with the clean clock signal.

Abstract translation: 在一个实施例中，存储器接口包括被配置为接收参考时钟信号的清理锁相环（PLL），并且基于参考时钟信号产生干净的时钟信号。 存储器接口还包括被配置为接收数据，数据时钟信号和干净时钟信号的同步电路，其中同步电路还被配置为使用数据时钟信号对数据进行采样，并使采样数据与干净的 时钟信号。