MEMORY TRANSACTION MANAGEMENT
    2.
    发明申请

    公开(公告)号:WO2023069828A1

    公开(公告)日:2023-04-27

    申请号:PCT/US2022/077131

    申请日:2022-09-28

    Abstract: A device includes a processor coupled to a memory. The processor is configured to assign distinct domain identifiers to each of multiple software threads. The processor is also configured to control operation of one or more components of the processor based on a number of memory transactions associated with a domain identifier.

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