公开(公告)号：WO2017171992A1

公开(公告)日：2017-10-05

申请号：PCT/US2017/014709

申请日：2017-01-24

Applicant: QUALCOMM INCORPORATED

Inventor： KUMAR, Tushar ,  JIA, Wenhao ,  RAMAN, Arun ,  CHAO, Hui ,  RUAN, Wenjia

IPC: G06T3/40

Abstract: Various embodiments may include methods executed by processors of computing devices for geometry based work execution prioritization. The processor may receive events, such as images. The processor may overlay a boundary shape on the event to identify discard regions of the event lying outside the boundary shape. The processor may identify work regions of the events lying within the working boundary shape. The devices may determine a cancellation likelihood for each of the identified work regions of the events. The processor may assign a trimming weight to each of the identified work regions based on the determined cancellation likelihoods. The processor may then add each of the identified work regions as a work item to an execution work list in an order based on the assigned trimming weights. The work items may be processed in order of trimming weight priority.

公开(公告)号：WO2017034738A1

公开(公告)日：2017-03-02

申请号：PCT/US2016/044168

申请日：2016-07-27

Applicant: QUALCOMM INCORPORATED

Inventor： SUAREZ GRACIA, Dario ,  KUMAR, Tushar ,  NATARAJAN, Aravind ,  HASTANTRAM, Ravish ,  CASCAVAL, Gheorghe Calin ,  ZHAO, Han

IPC: G06F9/50 ,  G06F9/48 ,  G06F11/34 ,  G06F12/0862 ,  G06F12/12 ,  G06F12/0806

CPC classification number: G06F9/48 ,  G06F9/4806 ,  G06F9/4831 ,  G06F9/4837 ,  G06F9/4843 ,  G06F9/4881 ,  G06F9/4893 ,  G06F9/50 ,  G06F9/5005 ,  G06F9/5011 ,  G06F9/5016 ,  G06F9/5022 ,  G06F9/5027 ,  G06F9/5033 ,  G06F9/5038 ,  G06F9/5044 ,  G06F9/505 ,  G06F9/5055 ,  G06F9/5083 ,  G06F9/5094 ,  G06F11/3419 ,  G06F11/3466 ,  G06F12/0806 ,  G06F12/0862 ,  G06F12/12 ,  G06F12/128 ,  G06F2212/1016 ,  G06F2212/62 ,  Y02D10/22 ,  Y02D10/24

Abstract: Various embodiments include methods for data management in a computing device utilizing a plurality of processing units. Embodiment methods may include generating a data transfer heuristic model based on measurements from a plurality of sample data transfers between a plurality of data storage units. The generated data transfer heuristic model may be used to calculate data transfer costs for each of a plurality of tasks. The calculated data transfer costs may be used to schedule execution of the plurality of tasks in an execution order on selected ones of the plurality of processing units. The data transfer heuristic model may be updated based on measurements of data transfers occurring during the executions of the plurality of tasks (e.g., time, power consumption, etc.). Code executing on the processing units may indicate to a runtime when certain data blocks are no longer needed and thus may be evicted and/or pre-fetched for others.

Abstract translation: 各种实施例包括利用多个处理单元的计算设备中的数据管理方法。 实施方式可以包括基于来自多个数据存储单元之间的多个采样数据传输的测量来生成数据传输启发式模型。 生成的数据传输启发式模型可用于计算多个任务中的每一个的数据传输成本。 所计算的数据传输成本可以用于以多个处理单元中的选定的处理单元的执行顺序调度多个任务的执行。 可以基于在执行多个任务期间发生的数据传输的测量（例如，时间，功耗等）来更新数据传输启发式模型。 在处理单元上执行的代码可以在不再需要某些数据块的情况下向运行时指示，并且因此可以被驱逐和/或预取其他数据块。

公开(公告)号：WO2017127180A1

公开(公告)日：2017-07-27

申请号：PCT/US2016/066319

申请日：2016-12-13

Applicant: QUALCOMM INCORPORATED

Inventor： KUMAR, Tushar ,  NATARAJAN, Aravind ,  SUAREZ GRACIA, Dario

IPC: G06F9/46

CPC classification number: G06F3/0656 ,  G06F3/061 ,  G06F3/0673 ,  G06F9/3834 ,  G06F9/467 ,  G06F9/544 ,  G06F12/1072 ,  G06F2212/65

Abstract: Methods, devices, and non-transitory processor-readable storage media for a computing device to merge concurrent writes from a plurality of processing units to a buffer associated with an application. An embodiment method executed by a processor may include identifying a plurality of concurrent requests to access the buffer that are sparse, disjoint, and write-only, configuring a write-set for each of the plurality of processing units, executing the plurality of concurrent requests to access the buffer using the write-sets, determining whether each of the plurality of concurrent requests to access the buffer is complete, obtaining a buffer index and data via the write-set of each of the plurality of processing units, and writing to the buffer using the received buffer index and data via the write-set of each of the plurality of processing units in response to determining that each of the plurality of concurrent requests to access the buffer is complete.

Abstract translation: 用于计算设备的方法，设备和非暂时性处理器可读存储介质将来自多个处理单元的并发写入合并到与应用相关联的缓冲区。 由处理器执行的实施例方法可以包括：识别访问缓冲区的多个并发请求，所述并发请求是稀疏的，不相交的和只写的;为多个处理单元中的每一个配置写集;执行多个并发请求 使用所述写入集访问所述缓冲器，确定所述多个访问所述缓冲器的并发请求中的每一个是否完成，经由所述多个处理单元中的每一个的所述写入集获得缓冲器索引和数据，以及写入 响应于确定访问缓冲器的多个并发请求中的每一个都完成，使用所接收的缓冲器索引和数据经由多个处理单元中的每一个的写入集合来缓冲所述缓冲器。

公开(公告)号：WO2017065913A1

公开(公告)日：2017-04-20

申请号：PCT/US2016/051708

申请日：2016-09-14

Applicant: QUALCOMM INCORPORATED

Inventor： RAMAN, Arun ,  KUMAR, Tushar

IPC: G06F9/52

CPC classification number: G06F9/524 ,  G06F9/5027 ,  G06F9/52

Abstract: Embodiments include computing devices, apparatus, and methods implemented by a computing device for task scheduling in the presence of task conflict edges on a computing device. The computing device may determine whether a first task and a second task are related by a task conflict edge. In response to determining that the first task and the second task are related by the task conflict edge, the computing device may determine whether the second task acquires a resource required for execution of the first task and the second task. In response to determining that the second task fails to acquire the resource, the computing device may assign a dynamic task dependency edge from the first task to the second task.

Abstract translation: 实施例包括由计算设备实现的计算设备，装置和方法，用于在计算设备上存在任务冲突边缘时进行任务调度。 计算设备可以通过任务冲突边缘确定第一任务和第二任务是否相关。 响应于通过任务冲突边缘确定第一任务和第二任务相关，计算设备可确定第二任务是否获取执行第一任务和第二任务所需的资源。 响应于确定第二任务未能获取资源，计算设备可以将动态任务依赖性边缘从第一任务分配给第二任务。

公开(公告)号：EP3497563A1

公开(公告)日：2019-06-19

申请号：EP17729596.1

申请日：2017-05-23

Applicant: Qualcomm Incorporated

Inventor： RUAN, Wenjia ,  ZHAO, Han ,  KUMAR, Tushar

IPC: G06F9/48 ,  G06F1/32 ,  G06F9/50

公开(公告)号：EP3362898A1

公开(公告)日：2018-08-22

申请号：EP16770189.5

申请日：2016-09-14

Applicant: Qualcomm Incorporated

Inventor： RAMAN, Arun ,  KUMAR, Tushar

IPC: G06F9/52

CPC classification number: G06F9/524 ,  G06F9/5027 ,  G06F9/52

Abstract: Embodiments include computing devices, apparatus, and methods implemented by a computing device for task scheduling in the presence of task conflict edges on a computing device. The computing device may determine whether a first task and a second task are related by a task conflict edge. In response to determining that the first task and the second task are related by the task conflict edge, the computing device may determine whether the second task acquires a resource required for execution of the first task and the second task. In response to determining that the second task fails to acquire the resource, the computing device may assign a dynamic task dependency edge from the first task to the second task.

公开(公告)号：EP3362893A1

公开(公告)日：2018-08-22

申请号：EP16770195.2

申请日：2016-09-14

Applicant: Qualcomm Incorporated

Inventor： RAMAN, Arun ,  KUMAR, Tushar

IPC: G06F9/48

CPC classification number: G06F9/52 ,  G06F9/4881 ,  G06F17/30424 ,  G06F17/30958

Abstract: Embodiments include computing devices, apparatus, and methods implemented by a computing device for accelerating execution of a plurality of tasks belonging to a common property task graph. The computing device may identify a first successor task dependent upon a bundled task such that an available synchronization mechanism is a common property for the bundled task and the first successor task, and such that the first successor task only depends upon predecessor tasks for which the available synchronization mechanism is a common property. The computing device may add the first successor task to a common property task graph and add the plurality of tasks belonging to the common property task graph to a ready queue. The computing device may recursively identify successor tasks. The synchronization mechanism may include a synchronization mechanism for control logic flow or a synchronization mechanism for data access.

公开(公告)号：WO2017172205A1

公开(公告)日：2017-10-05

申请号：PCT/US2017/020164

申请日：2017-03-01

Applicant: QUALCOMM INCORPORATED

Inventor： SUAREZ GRACIA, Dario ,  CASCAVAL, Gheorghe ,  ZHAO, Han ,  KUMAR, Tushar ,  NATARAJAN, Aravind ,  RAMAN, Arun

IPC: G06F9/52

CPC classification number: G06F9/52 ,  G06F9/46

Abstract: Embodiments include computing devices, systems, and methods identifying enhanced synchronization operation outcomes. A computing device may receive a first resource access request for a first resource of a computing device including a first requester identifier from a first computing element of the computing device. The computing device may also receive a second resource access request for the first resource including a second requester identifier from a second computing element of the computing device. The computing device may grant the first computing element access to the first resource based on the first resource access request, and return a response to the second computing element including the first requester identifier as a winner computing element identifier.

Abstract translation: 实施例包括识别增强的同步操作结果的计算设备，系统和方法。 计算设备可以从计算设备的第一计算元件接收针对包括第一请求者标识符的计算设备的第一资源的第一资源访问请求。 计算设备还可以从计算设备的第二计算元件接收针对包括第二请求者标识符的第一资源的第二资源访问请求。 计算设备可以基于第一资源访问请求向第一计算元件授予对第一资源的访问权，并且向第二计算元件返回包括第一请求者标识符的响应作为获胜者计算元件标识符。

公开(公告)号：WO2017171994A1

公开(公告)日：2017-10-05

申请号：PCT/US2017/014715

申请日：2017-01-24

Applicant: QUALCOMM INCORPORATED

Inventor： KUMAR, Tushar ,  JIA, Wenhao ,  RAMAN, Arun ,  CHAO, Hui ,  RUAN, Wenjia

IPC: G06T3/40

Abstract: Various embodiments may include methods executed by processors of computing devices for geometry based work execution prioritization. The processor may receive events, such as images. The processor may overlay a boundary shape on the event to identify discard regions of the event lying outside the boundary shape. The processor may identify work regions of the events lying within the working boundary shape. The devices may determine a cancellation likelihood for each of the identified work regions of the events. The processor may assign a trimming weight to each of the identified work regions based on the determined cancellation likelihoods. The processor may then add each of the identified work regions as a work item to an execution work list in an order based on the assigned trimming weights. The work items may be processed in order of trimming weight priority.

Abstract translation: 各种实施例可以包括由用于基于几何的工作执行优先化的计算设备的处理器执行的方法。 处理器可能接收事件，如图像。 处理器可以在事件上覆盖边界形状以识别位于边界形状之外的事件的丢弃区域。 处理器可以识别位于工作边界形状内的事件的工作区域。 设备可以确定事件的每个识别的工作区域的消除可能性。 处理器可以基于确定的消除可能性向每个所识别的工作区域分配修剪权重。 处理器然后可以基于所分配的修剪权重将每个所识别的工作区域作为工作项目添加到执行工作列表中。 工作项目可以按照修剪重量优先顺序进行处理。

公开(公告)号：WO2017065915A1

公开(公告)日：2017-04-20

申请号：PCT/US2016/051739

申请日：2016-09-14

Applicant: QUALCOMM INCORPORATED

Inventor： RAMAN, Arun ,  KUMAR, Tushar

IPC: G06F9/48

CPC classification number: G06F9/52 ,  G06F9/4881 ,  G06F17/30424 ,  G06F17/30958

Abstract: Embodiments include computing devices, apparatus, and methods implemented by a computing device for accelerating execution of a plurality of tasks belonging to a common property task graph. The computing device may identify a first successor task dependent upon a bundled task such that an available synchronization mechanism is a common property for the bundled task and the first successor task, and such that the first successor task only depends upon predecessor tasks for which the available synchronization mechanism is a common property. The computing device may add the first successor task to a common property task graph and add the plurality of tasks belonging to the common property task graph to a ready queue. The computing device may recursively identify successor tasks. The synchronization mechanism may include a synchronization mechanism for control logic flow or a synchronization mechanism for data access.

Abstract translation: 实施例包括由计算设备实现的用于加速属于公共属性任务图的多个任务的执行的计算设备，装置和方法。 计算设备可以根据捆绑任务来识别第一后继任务，使得可用同步机制是捆绑任务和第一后继任务的公共属性，并且使得第一后继任务仅取决于可用的前任任务 同步机制是一个共同的属性。 计算设备可以将第一后继任务添加到公共属性任务图并且将属于公共属性任务图的多个任务添加到就绪队列。 计算设备可以递归地识别后续任务。 同步机制可以包括用于控制逻辑流程的同步机制或用于数据访问的同步机制。