Abstract:
An apparatus to determine the inverse transform of a block of encoded data, the block of encoded data comprising a plurality of compressed frequency domain data elements. An input register (332) is configured to receive a predetermined quantity of data elements. At least one butterfly processor (364) is coupled to the input register and is configured to perform at least one mathematical operation on selected pairs of data elements to produce an output of processed data elements. At least one intermediate register (340) is coupled to the butterfly processor and configured to temporarily store the processed data. A feedback loop is coupled to the intermediate register and the butterfly processor, and if enabled, is configured to transfer a first portion of processed data elements to the appropriate butterfly processor to perform additional mathematical operations and where if disabled, is configured to transfer a second portion of processed data elements to at least one holding register.
Abstract:
Apparatus and method for selecting an appropriate parameter at decompression are disclosed. In particular, when adaptive block size discrete cosine transform compression is used to compress data, different combinations of sub-blocks can be generated. To decompress the different combinations of sub-blocks, the appropriate parameter is selected based on block size assignment information and the address of data in the data block.
Abstract:
An apparatus to determine a transform of a block of encoded data the block of encoded data comprising a plurality of data elements. An input register is configured to receive a predetermined quantity of data elements. At least one butterfly processor is coupled to the input register and is configured to perform at least one mathematical operation on selected pairs of data elements to produce an output of processed data elements. At least one intermediate register is coupled to the butterfly processor and configured to temporarily store the processed data. A feedback loop is coupled to the intermediate register and the butterfly processor, and where if enabled, is configured to transfer a first portion of processed data elements to the appropriate butterfly processor to perform additional mathematical operations and where if disabled, is configured to transfer a second portion of processed data elements to at least one holding register.
Abstract:
The present invention discloses a variable rate transmission system wherein a packet of variable rate data is modulated in accordance with a traffic channel sequence supplied by a traffic PN generator (63) if the capacity of said traffic channel is greater than or equal to said data rate of the packet. If the capacity of said traffic channel is less than said data rate, the packet of variable rate data is modulated in accordance with the traffic channel sequence supplied by the traffic PN generator (63) and in accordance with at least one overflow channel sequence supplied by an overflow channel generator (65). The present invention further discloses a receiving system for receiving variable rate data where a received packet of variable rate data is demodulated in accordance with a traffic channel sequence supplied by a traffic PN generator (104) if the capacity of said traffic channel is greater than or equal to a data rate of said packet. If the capacity of said traffic channel is less than said data rate of the packet of variable rate data, the received packet is demodulated in accordance with a traffic channel sequence supplied by a traffic PN generator (104) and in accordance with at least one overflow channel sequence supplied by an overflow channel generator (120).
Abstract:
An apparatus to determine a transform of a block of encoded data the block of encoded data comprising a plurality of data elements. An input register is configured to receive a predetermined quantity of data elements. At least one butterfly processor is coupled to the input register and is configured to perform at least one mathematical operation on selected pairs of data elements to produce an output of processed data elements. At least one intermediate register is coupled to the butterfly processor and configured to temporarily store the processed data. A feedback loop is coupled to the intermediate register and the butterfly processor, and where if enabled, is configured to transfer a first portion of processed data elements to the appropriate butterfly processor to perform additional mathematical operations and where if disabled, is configured to transfer a second portion of processed data elements to at least one holding register.
Abstract:
The present invention discloses a variable rate transmission system wherein a packet of variable rate data is modulated in accordance with a traffic channel sequence supplied by a traffic PN generator (63) if the capacity of said traffic channel is greater than or equal to said data rate of the packet. If the capacity of said traffic channel is less than said data rate, the packet of variable rate data is modulated in accordance with the traffic channel sequence supplied by the traffic PN generator (63) and in accordance with at least one overflow channel sequence supplied by an overflow channel generator (65). The present invention further discloses a receiving system for receiving variable rate data where a received packet of variable rate data is demodulated in accordance with a traffic channel sequence supplied by a traffic PN generator (104) if the capacity of said traffic channel is greater than or equal to a data rate of said packet. If the capacity of said traffic channel is less than said data rate of the packet of variable rate data, the received packet is demodulated in accordance with a traffic channel sequence supplied by a traffic PN generator (104) and in accordance with at least one overflow channel sequence supplied by an overflow channel generator (120).
Abstract:
The present invention discloses a variable rate transmission system wherein a packet of variable rate data is modulated in accordance with a traffic channel sequence supplied by a traffic PN generator (63) if the capacity of said traffic channel is greater than or equal to said data rate of the packet. If the capacity of said traffic channel is less than said data rate, the packet of variable rate data is modulated in accordance with the traffic channel sequence supplied by the traffic PN generator (63) and in accordance with at least one overflow channel sequence supplied by an overflow channel generator (65). The present invention further discloses a receiving system for receiving variable rate data where a received packet of variable rate data is demodulated in accordance with a traffic channel sequence supplied by a traffic PN generator (104) if the capacity of said traffic channel is greater than or equal to a data rate of said packet. If the capacity of said traffic channel is less than said data rate of the packet of variable rate data, the received packet is demodulated in accordance with a traffic channel sequence supplied by a traffic PN generator (104) and in accordance with at least one overflow channel sequence supplied by an overflow channel generator (120).
Abstract:
Apparatus and method for selecting an appropriate parameter at decompression are disclosed. In particular, when adaptive block size discrete cosine transform compression is used to compress data, different combinations of sub-blocks can be generated. To decompress the different combinations of sub-blocks, the appropriate parameter is selected based on block size assignment information and the address of data in the data block.
Abstract:
An apparatus to determine a transform of a block of encoded data the block of encoded data comprising a plurality of data elements. An input register is configured to receive a predetermined quantity of data elements. At least one butterfly processor is coupled to the input register and is configured to perform at least one mathematical operation on selected pairs of data elements to produce an output of processed data elements. At least one intermediate register is coupled to the butterfly processor and configured to temporarily store the processed data. A feedback loop is coupled to the intermediate register and the butterfly processor, and where if enabled, is configured to transfer a first portion of processed data elements to the appropriate butterfly processor to perform additional mathematical operations and where if disabled, is configured to transfer a second portion of processed data elements to at least one holding register.