公开(公告)号：WO2012047692A1

公开(公告)日：2012-04-12

申请号：PCT/US2011/053615

申请日：2011-09-28

Applicant: QUALCOMM INCORPORATED ,  MARCU, Cristian ,  SAVOJ, Jafar

Inventor： MARCU, Cristian ,  SAVOJ, Jafar

IPC: G06K7/00 ,  G06K19/07 ,  H03D1/14

CPC classification number: H03D3/00 ,  G06K7/0008 ,  G06K7/10237 ,  G06K19/0723 ,  Y10T29/49016 ,  Y10T29/49117

Abstract: A differential input envelope detector receives an unamplified Near Field Communication (NFC) input signal from an NFC antenna and downconverts an NFC intelligence signal to baseband. In one example, the NFC input signal includes the NFC intelligence signal modulated onto a carrier. The differential input envelope detector downconverts and outputs the downconverted NFC intelligence signal onto an output node in such a way that the fundamental and odd harmonics of the carrier are canceled on the output node. There is substantially no signal of the frequency of the carrier present on the output node and this facilitates filtering of the downconverted NFC intelligence signal from interference and data recovery. An NFC data recovery circuit receives the downconverted NFC intelligence signal from the envelope detector output node. The NFC data recovery circuit can be a low power digital circuit involving an ultra-low power ADC and subsequent low power digital processing circuitry.

Abstract translation: 差分输入包络检测器从NFC天线接收未放大的近场通信（NFC）输入信号，并将NFC智能信号下变频到基带。 在一个示例中，NFC输入信号包括调制到载波上的NFC智能信号。 差分输入包络检测器将下变频的NFC智能信号下变频并输出到输出节点上，使得在输出节点上消除载波的基波和奇次谐波。 输出节点上基本上没有存在载波频率的信号，这有助于滤波下变频NFC智能信号的干扰和数据恢复。 NFC数据恢复电路从包络检测器输出节点接收经下变频的NFC智能信号。 NFC数据恢复电路可以是涉及超低功率ADC和随后的低功率数字处理电路的低功率数字电路。

公开(公告)号：WO2011156622A1

公开(公告)日：2011-12-15

申请号：PCT/US2011/039835

申请日：2011-06-09

Applicant: QUALCOMM Incorporated ,  KRISHNAN, Koushik ,  SAVOJ, Jafar

Inventor： KRISHNAN, Koushik ,  SAVOJ, Jafar

IPC: H03L7/099 ,  H03K5/13 ,  H03K23/68

CPC classification number: H03L7/0996 ,  H03K23/005 ,  H03K23/68

Abstract: Methods and apparatus for a gray-coded phase rotating frequency divider. A phase selector is provided that includes two or more selectors, each selector configured to receive multiple clock phases and output a respective clock phase based on one or more selection bits that are part of a selection input, and a gray code generator configured to generate a gray coded output that forms the selection input so that when the gray coded output changes state only selection bits associated with a single selector change. A method includes grouping a plurality of clock phases into two or more groups, for each group, selecting a respective clock phase based on one or more selection bits that are part of a selection input, and generating a gray coded output that forms the selection input so that when the gray coded output changes state only selection bits associated with a single group change.

Abstract translation: 灰色相位旋转分频器的方法和装置。 提供一种相位选择器，其包括两个或多个选择器，每个选择器被配置为接收多个时钟相位，并且基于作为选择输入的一部分的一个或多个选择位输出相应的时钟相位;以及灰色代码生成器， 灰色编码输出形成选择输入，使得当灰度编码输出仅改变与单个选择器改变相关联的选择位的状态。 一种方法包括对于每个组将多个时钟相位分成两组或多组，基于作为选择输入的一部分的一个或多个选择位选择相应的时钟相位，并且生成形成选择输入的灰度编码输出 使得当灰度编码输出仅改变与单个组相关联的选择位的状态改变时。

公开(公告)号：WO2013063517A1

公开(公告)日：2013-05-02

申请号：PCT/US2012/062292

申请日：2012-10-26

Applicant: QUALCOMM INCORPORATED

Inventor： SAVOJ, Jafar

IPC: G06K7/10

CPC classification number: G06K7/10237

Abstract: A near field communication device (NFC transceiver) comprises a current digital-to-analog converter (current DAC) configured to convey a current to an antenna in a first active near-field communication- mode. Load modulation is used by the NFC device in a second passive communication mode for sending data. For effecting load modulation, components of the current DAC are used as modulation loads.

Abstract translation: 近场通信设备（NFC收发器）包括被配置为以第一主动近场通信模式将电流传送到天线的当前数模转换器（电流DAC）。 负载调制由NFC设备以第二无源通信模式用于发送数据。 为了实现负载调制，电流DAC的组件用作调制负载。

公开(公告)号：WO2013063514A2

公开(公告)日：2013-05-02

申请号：PCT/US2012/062286

申请日：2012-10-26

Applicant: QUALCOMM INCORPORATED

Inventor： MARCU, Cristian ,  SAVOJ, Jafar

IPC: G06K7/00 ,  G06K19/07

CPC classification number: G06K7/0008 ,  G06K19/0723

Abstract: Exemplary embodiments are directed to adaptive signal scaling in NFC transceivers. A transceiver may include a programmable load modulation element configured for load modulation in a tag mode. Further, the transceiver may include a sensing element for measuring an amount of power harvested by the transceiver in the tag mode. The transceiver may also include a controller configured for adjusting a depth of load modulation of the programmable load modulation element depending on the amount of power harvested.

Abstract translation: 示例性实施例涉及NFC收发器中的自适应信号缩放。 收发器可以包括被配置用于以标签模式进行负载调制的可编程负载调制元件。 此外，收发器可以包括感测元件，用于测量在标签模式中由收发器收获的功率的量。 收发器还可以包括控制器，该控制器被配置为根据收集的功率量来调整可编程负载调制元件的负载调制深度。

公开(公告)号：WO2011072081A1

公开(公告)日：2011-06-16

申请号：PCT/US2010/059577

申请日：2010-12-08

Applicant: QUALCOMM INCORPORATED ,  SOLTANIAN, Babak ,  SAVOJ, Jafar

Inventor： SOLTANIAN, Babak ,  SAVOJ, Jafar

IPC: H03K3/356

CPC classification number: H03K3/356156 ,  H03K3/356121

Abstract: A quadrature output (IP, IN, QP, QN) high-frequency RF divide-by-two circuit (129) includes a pair of differential complementary logic latches (142, 143). The latches are interconnected to form a toggle flip-flop (200). Each latch (200) includes a tracking cell and a locking cell. In a first embodiment (200), the locking cell includes two complementary logic inverters (201, 205, 203, 207) and two transmission gates (202, 206; 204, 208). When the locking cell is locked, the two gates (211, 213; 212, 214) are enabled such that the locked (i.e., latched) signal passes through both transmission gates and both inverters. In one advantageous aspect, the tracking cell only involves two transmission gates (211, 213; 212, 214). Due to the circuit topology, the first embodiment is operable from a low supply voltage at a high operating frequency while consuming a low amount of supply current. In a second (300) and third embodiment (400), the tracking cell involves a pair of inverters ((301, 304; 302, 305) or (401, 404; 402, 405)). The sources of the transistors of the inverters are, however, coupled together thereby resulting in performance advantages over conventional circuits.

Abstract translation: 正交输出（IP，IN，QP，QN）高频RF分频电路（129）包括一对差分互补逻辑锁存器（142,143）。 锁存器互连以形成切换触发器（200）。 每个锁存器（200）包括跟踪单元和锁定单元。 在第一实施例（200）中，锁定单元包括两个互补逻辑反相器（201,205,203,207）和两个传输门（202,206; 204,208）。 当锁定单元被锁定时，两个门（211,213,212,214）被使能使得锁定（即锁存的）信号通过两个传输门和两个逆变器。 在一个有利的方面，跟踪单元仅涉及两个传输门（211,213; 212,214）。 由于电路拓扑结构，第一实施例可以在高工作频率的低电源电压下工作，同时消耗低的电源电流。 在第二（300）和第三实施例（400）中，跟踪单元涉及一对逆变器（（301,304,302,305）或（401,404; 402,405））。 然而，逆变器的晶体管的源极耦合在一起，从而导致相对于常规电路的性能优点。

公开(公告)号：WO2010151800A2

公开(公告)日：2010-12-29

申请号：PCT/US2010/040043

申请日：2010-06-25

Applicant: QUALCOMM Incorporated ,  AHMADI, Mahmoud R. ,  SAVOJ, Jafar

Inventor： AHMADI, Mahmoud R. ,  SAVOJ, Jafar

IPC: H03L7/089

CPC classification number: H03L7/0891 ,  H03L7/1976

Abstract: A method for reducing noise in a frequency synthesizer includes selecting a design variable k , calibrating a feedback time delay (T d ), such that T d = k T VCO , where T VCO is the period of the synthesizer output signal. The method further includes estimating an instantaneous quantization error to a number of bits equal to q , defining a reference bias current of I cp /( k 2 q ), where I cp is a charge pump current signal, and applying the estimated instantaneous quantization error to a current array to produce a down modification signal (ΔI). The current array is biased by the reference bias current. The down modification signal (ΔI) is summed with the charge pump current signal I cp to modulate a down current portion of the charge pump current signal I cp .

Abstract translation: 一种用于降低频率合成器中的噪声的方法，包括选择设计变量k，校准反馈时间延迟（Td），使得Td = kTVCO，其中TVCO是合成器输出信号的周期。 该方法还包括将瞬时量化误差估计为等于q的位数，定义Icp /（k2q）的参考偏置电流，其中Icp是电荷泵电流信号，并将估计的瞬时量化误差应用于电流 阵列以产生降维修信号（ΔI）。 电流阵列被参考偏置电流偏置。 降频修正信号（ΔI）与电荷泵电流信号Icp相加，以调制电荷泵电流信号Icp的下降电流部分。

公开(公告)号：EP2771840A1

公开(公告)日：2014-09-03

申请号：EP12784842.2

申请日：2012-10-26

Applicant: Qualcomm Incorporated

Inventor： SAVOJ, Jafar

IPC: G06K7/10

CPC classification number: G06K7/10237

Abstract: A near field communication device (NFC transceiver) comprises a current digital-to-analog converter (current DAC) configured to convey a current to an antenna in a first active near-field communication- mode. Load modulation is used by the NFC device in a second passive communication mode for sending data. For effecting load modulation, components of the current DAC are used as modulation loads.

Abstract translation: 示范性实施例涉及近场通信设备可以包括被配置为在第一近场通信（NFC）模式中将电流传送到天线的当前数模转换器（DAC），并使得能够在第二个场中进行负载调制 NFC模式。

公开(公告)号：WO2013063503A2

公开(公告)日：2013-05-02

申请号：PCT/US2012/062271

申请日：2012-10-26

Applicant: QUALCOMM INCORPORATED

Inventor： SAVOJ, Jafar ,  WONG, Angelica

IPC: G06K7/00 ,  G06K19/077

CPC classification number: G06K19/07749 ,  G06K7/0008

Abstract: Exemplary embodiments are directed to a transceiver having an adaptive matching circuit. A transceiver may include a matching circuit that is coupled to an antenna and includes an adjustable capacitor. The transceiver may further include an envelope detector coupled to the antenna and a sensor for sensing a voltage at an output of the envelope detector.

Abstract translation: 示例性实施例针对具有自适应匹配电路的收发器。 收发器可以包括耦合到天线并且包括可调电容器的匹配电路。 收发器还可以包括耦合到天线的包络检测器和用于感测包络检测器的输出处的电压的传感器。

公开(公告)号：WO2013063500A3

公开(公告)日：2013-05-02

申请号：PCT/US2012/062268

申请日：2012-10-26

Applicant: QUALCOMM INCORPORATED

Inventor： SAVOJ, Jafar

IPC: H04L7/033 ,  H04L7/10 ,  H03L7/089 ,  H04B5/00 ,  H04L27/02 ,  G06K7/00

Abstract: Exemplary embodiments are directed to data and clock recovery in NFC transceivers. A transceiver may include a phase-locked loop configured to recover a clock from a received input signal in a first mode and enable for oversampling of an output signal in a second, different mode.

公开(公告)号：WO2012068326A1

公开(公告)日：2012-05-24

申请号：PCT/US2011/061115

申请日：2011-11-17

Applicant: QUALCOMM Incorporated ,  SOLTANIAN, Babak ,  SAVOJ, Jafar

Inventor： SOLTANIAN, Babak ,  SAVOJ, Jafar

IPC: H03L7/16 ,  H04B1/00

CPC classification number: H04B1/40 ,  H03L7/099 ,  H03L7/104 ,  H03L7/16 ,  H03L7/193 ,  H03L7/1976 ,  H04B1/0082

Abstract: A VCO of a PLL outputs a first differential signal of frequency FVCO. A first divide-by-two circuit local to the VCO divides the first differential signal and outputs a first quadrature signal of frequency FVCO/2. Two of the component signals of the first quadrature signal are routed to a second divide-by-two circuit local to a first mixer of a first device. The second divide-by-two circuit outputs a second quadrature signal of frequency FVCO/4 to the first mixer. All four signals of the first quadrature signal of frequency FVCO/2 are routed through phase mismatch correction circuitry to a second mixer of a second device. In one example, FVCO is a tunable frequency of about ten gigahertz, the first device is an IEEE802.11b/g transmitter or receiver that transmits or receives in a first band, and the second device is an IEEE802.11a transmitter or receiver that transmits or receives in a second band.

Abstract translation: PLL的VCO输出频率为FVCO的第一差分信号。 第一差分信号分频到VCO的局部区域，并输出频率为FVCO / 2的第一正交信号。 第一正交信号的分量信号中的两个被路由到第一设备的第一混频器本地的第二分频电路。 第二分频电路向第一混频器输出频率为FVCO / 4的第二正交信号。 频率为FVCO / 2的第一正交信号的所有四个信号通过相位失配校正电路被路由到第二装置的第二混频器。 在一个示例中，FVCO是约10千兆赫兹的可调频率，第一设备是在第一频带中发送或接收的IEEE802.11b / g发射机或接收机，第二设备是IEEE802.11a发射机或接收机， 或接收在第二频带。