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公开(公告)号：WO2014011948A1
公开(公告)日：2014-01-16
申请号：PCT/US2013/050181
申请日：2013-07-12
Applicant: QUALCOMM INCORPORATED
Inventor： GOHARI, Amir Aminzadeh , MAHESHWARI, Shailesh , URGAONKAR, Sandeep , MITRA, Alok , RUMI, Mohammed M. , KUMAR, Vaibhav , BABBAR, Uppinder Singh , KLINGENBRUNN, Thomas , NGUYEN, Bao Vinh , KOHLENZ, Mathias , SHEORAN, Gautam , TERASAWA, Daisuke , FINLAY, Iain
IPC: H04L1/00
CPC classification number: H04W24/02 , H04L1/0052 , H04L1/0061
Abstract: Aspects of the present disclosure provide methods and apparatus for offloading checksum processing in a user equipment (UE) (e.g., from an application processor to a modem processor). Such offloading may speed up packet processing, increase data rate, and/or free up resources of the application processor for other tasks.
Abstract translation: 本公开的方面提供了用于在用户设备（UE）（例如，从应用处理器到调制解调器处理器）中卸载校验和处理的方法和装置。 这种卸载可以加速数据包处理，提高数据速率，和/或释放应用处理器的资源以用于其他任务。
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2.发明申请
公开(公告)号：WO2010087865A1
公开(公告)日：2010-08-05
申请号：PCT/US2009/035580
申请日：2009-02-27
Applicant: QUALCOMM INCORPORATED , KOHLENZ, Mathias , KHAN, Irfan A. , MIR, Idreas A. , SATHYANARAYAN, Madhusudan , MAHESHWARI, Shailesh , KRISHNAMOORTHY, Srividhya , URGAONKAR, Sandeep , KLINGENBRUNN, Thomas , LIOU, Tynghuei
Inventor： KOHLENZ, Mathias , KHAN, Irfan A. , MIR, Idreas A. , SATHYANARAYAN, Madhusudan , MAHESHWARI, Shailesh , KRISHNAMOORTHY, Srividhya , URGAONKAR, Sandeep , KLINGENBRUNN, Thomas , LIOU, Tynghuei
CPC classification number: H04L63/0428 , H04L1/0045 , H04L9/065 , H04L63/16 , H04L69/324 , H04L69/325 , H04L69/326 , H04L2209/12 , H04L2209/80
Abstract: Techniques for processing data for a set of protocols at a transmitter and a receiver are described. In one exemplary embodiment, the receiver decodes received frames to obtain decoded MAC frames, obtains un-ordered RLC frames from the decoded MAC frames, and deciphers the un-ordered RLC frames to obtain deciphered RLC frames. In another exemplary embodiment, the receiver computes partial checksums for RLC frames, computes checksums for IP headers, and computes checksums for TCP/UDP frames based on the partial checksums for the RLC frames and the checksums for the IP headers. In yet another exemplary embodiment, the transmitter generates MAC and RLC headers in a fast memory, transfers these header to an internal memory, retrieves a block of data from an external memory in a single transaction, moves the block of data and the RLC headers to form RLC frames, and moves the RLC frames and MAC headers to form MAC frames.
Abstract translation: 描述了用于在发射机和接收机处理一组协议的数据的技术。 在一个示例性实施例中，接收机解码接收的帧以获得解码的MAC帧，从解码的MAC帧获得未排序的RLC帧，并解密未排序的RLC帧以获得被解密的RLC帧。 在另一个示例性实施例中，接收机计算RLC帧的部分校验和，计算IP报头的校验和，并且基于RLC帧的部分校验和和IP报头的校验和来计算TCP / UDP帧的校验和。 在另一个示例性实施例中，发射机在快速存储器中生成MAC和RLC报头，将这些报头传送到内部存储器，在单个事务中从外部存储器检索数据块，将数据块和RLC报头移动到 形成RLC帧，并且移动RLC帧和MAC头以形成MAC帧。
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公开(公告)号：EP2465033A1
公开(公告)日：2012-06-20
申请号：EP10748172.3
申请日：2010-08-13
Applicant: Qualcomm Incorporated
Inventor： KOHLENZ, Mathias , KHAN, Irfan Anwar , SATHYANARAYAN, Madhusudan , MAHESHWARI, Shailesh , KRISHNAMOORTHY, Srividhya , URGAONKAR, Sandeep , KLINGENBRUNN, Thomas , LIOU, Tim Tynghuei , MIR, Idreas
IPC: G06F9/48
CPC classification number: G06F9/4843 , G06F9/3826 , G06F9/4812 , G06F9/5044 , Y02D10/22 , Y02D10/24
Abstract: Efficient data processing apparatus and methods include hardware components which are pre-programmed by software. Each hardware component triggers the other to complete its tasks. After the final pre-programmed hardware task is complete, the hardware component issues a software interrupt.
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Patent Agency Ranking
公开(公告)号：WO2011020053A1
公开(公告)日：2011-02-17
申请号：PCT/US2010/045517
申请日：2010-08-13
Applicant: QUALCOMM INCORPORATED , KOHLENZ, Mathias , KHAN, Irfan Anwar , SATHYANARAYAN, Madhusudan , MAHESHWARI, Shailesh , KRISHNAMOORTHY, Srividhya , URGAONKAR, Sandeep , KLINGENBRUNN, Thomas , LIOU, Tim Tynghuei , MIR, Idreas
Inventor： KOHLENZ, Mathias , KHAN, Irfan Anwar , SATHYANARAYAN, Madhusudan , MAHESHWARI, Shailesh , KRISHNAMOORTHY, Srividhya , URGAONKAR, Sandeep , KLINGENBRUNN, Thomas , LIOU, Tim Tynghuei , MIR, Idreas
IPC: G06F9/48
CPC classification number: G06F9/4843 , G06F9/3826 , G06F9/4812 , G06F9/5044 , Y02D10/22 , Y02D10/24
Abstract: Efficient data processing apparatus and methods include hardware components which are pre-programmed by software. Each hardware component triggers the other to complete its tasks. After the final pre-programmed hardware task is complete, the hardware component issues a software interrupt.
Abstract translation: 有效的数据处理装置和方法包括由软件预编程的硬件组件。 每个硬件组件触发另一个完成其任务。 最终的预编程硬件任务完成后，硬件组件发出软件中断。
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公开(公告)号：WO2011020051A1
公开(公告)日：2011-02-17
申请号：PCT/US2010/045515
申请日：2010-08-13
Applicant: QUALCOMM INCORPORATED , KOHLENZ, Mathias , MIR, Idreas , KHAN, Irfan Anwar , SATHYANARAYAN, Madhusudan , MAHESHWARI, Shailesh , KRISHNAMOORTHY, Srividhya , URGAONKAR, Sandeep , KLINGENBRUNN, Thomas , LIOU, Tim Tynghuei
Inventor： KOHLENZ, Mathias , MIR, Idreas , KHAN, Irfan Anwar , SATHYANARAYAN, Madhusudan , MAHESHWARI, Shailesh , KRISHNAMOORTHY, Srividhya , URGAONKAR, Sandeep , KLINGENBRUNN, Thomas , LIOU, Tim Tynghuei
IPC: G06F11/07 , G06F9/46 , G06F11/273
Abstract: An apparatus and method for distributed data processing is described herein. A main processor programs a mini-processor to process an incoming data stream. The mini-processor is located in close proximity to hardware components operating on the input data stream. A copy engine is also provided for copying data from multiple protocol data units in a single copy operation.
Abstract translation: 本文描述了用于分布式数据处理的装置和方法。 主处理器对微处理器进行编程以处理输入数据流。 迷你处理器位于靠近输入数据流操作的硬件组件上。 还提供了复制引擎，用于在单个复制操作中从多个协议数据单元复制数据。
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6.发明申请
公开(公告)号：WO2011020055A1
公开(公告)日：2011-02-17
申请号：PCT/US2010/045520
申请日：2010-08-13
Applicant: QUALCOMM Incorporated , KOHLENZ, Mathias , MIR, Idreas , KHAN, Irfan Anwar , SATHYANARAYAN, Madhusudan , MAHESHWARI, Shailesh , KRISHNAMOORTHY, Srividhya , URGAONKAR, Sandeep , KLINGENBRUNN, Thomas , LIOU, Tim Tynghuei
Inventor： KOHLENZ, Mathias , MIR, Idreas , KHAN, Irfan Anwar , SATHYANARAYAN, Madhusudan , MAHESHWARI, Shailesh , KRISHNAMOORTHY, Srividhya , URGAONKAR, Sandeep , KLINGENBRUNN, Thomas , LIOU, Tim Tynghuei
IPC: G06F9/50
CPC classification number: G06F9/5016 , Y02D10/22
Abstract: Multiple memory pools are defined in hardware for operating on data. At least one memory pool has a lower latency that the other memory pools. Hardware components operate directly on data in the lower latency memory pool.
Abstract translation: 硬件中定义了多个内存池，用于对数据进行操作。 至少一个内存池对其他内存池的延迟较低。 硬件组件直接对低延迟内存池中的数据进行操作。
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公开(公告)号：WO2011020046A1
公开(公告)日：2011-02-17
申请号：PCT/US2010/045510
申请日：2010-08-13
Applicant: QUALCOMM Incorporated , KOHLENZ, Mathias , MIR, Idreas , KHAN, Irfan Anwar , SATHYANARAYAN, Madhusudan , MAHESHWARI, Shailesh , KRISHNAMOORTHY, Srividhya , URGAONKAR, Sandeep , KLINGENBRUNN, Thomas , LIOU, Tim Tynghuei
Inventor： KOHLENZ, Mathias , MIR, Idreas , KHAN, Irfan Anwar , SATHYANARAYAN, Madhusudan , MAHESHWARI, Shailesh , KRISHNAMOORTHY, Srividhya , URGAONKAR, Sandeep , KLINGENBRUNN, Thomas , LIOU, Tim Tynghuei
IPC: H04L12/56
CPC classification number: H04L49/9005 , H04L49/90 , H04L49/901 , H04L49/9042
Abstract: Incoming data frames are parsed by a hardware component. Headers are extracted and stored in a first location along with a pointer to the associated payload. Payloads are stored in a single, contiguous memory location.
Abstract translation: 传入的数据帧由硬件组件解析。 标题被提取并存储在与指示相关联的有效载荷的指针的第一位置中。 有效载荷存储在单个连续的内存位置。
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8.发明公开
公开(公告)号：EP2465034A1
公开(公告)日：2012-06-20
申请号：EP10748173.1
申请日：2010-08-13
Applicant: Qualcomm Incorporated
Inventor： KOHLENZ, Mathias , MIR, Idreas , KHAN, Irfan Anwar , SATHYANARAYAN, Madhusudan , MAHESHWARI, Shailesh , KRISHNAMOORTHY, Srividhya , URGAONKAR, Sandeep , KLINGENBRUNN, Thomas , LIOU, Tim Tynghuei
IPC: G06F9/50
CPC classification number: G06F9/5016 , Y02D10/22
Abstract: Multiple memory pools are defined in hardware for operating on data. At least one memory pool has a lower latency that the other memory pools. Hardware components operate directly on data in the lower latency memory pool.
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