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公开(公告)号：WO2003038995A1
公开(公告)日：2003-05-08
申请号：PCT/US2002/034803
申请日：2002-10-29
Applicant: QUALCOMM INCORPORATED
Inventor： KLAREN, Jonathan , PERSICO, Charles, J. , WALTER, Scott , CHAN, Paul, L.
IPC: H03F3/72
CPC classification number: H03F3/602 , H03F3/72 , H03F2200/198
Abstract: A balanced power amplifier circuit arrangement comprises a driver amplifier stage (22) adapted to receive and amplify a signal. The amplified signal is input to a first coupler (26). The first coupler (26) produces an in-phase signal and an out-of-phase quadrature signal. A first power amplifier (38) receives and amplifies the in-phase signal. A second power amplifier (40) receives and amplifies the out-of-phase signal. A first switch (28) alternately connects an isolated port of the first coupler to ground (32) or a bypass path (36). A second coupler (42) receives and combines the amplified in-phase signal and the amplified out-of-phase signal to produce a combined signal. A second switch (30) alternately connects an isolated port of the second coupler (42) to either ground (34) or the bypass path (36). When the power amplifiers (38, 40) are powered down, the first coupler (26) splits the RF-signal into an in-phase signal and an out-of-phase signal. The power amplifiers (38, 40) appear as reflective impedances to the signal when they are powered down. Each signal reflects off the first and second power amplifiers (38, 40), respectively. The first coupler (26) combines the reflected signals and routes the combined signal through the bypass path (36) to the second coupler (42). The second coupler (42) splits the signal into an in-phase and out-of-phase signal and routes each to the power amplifiers (38, 40). The power amplifiers (38, 40) reflect each signal back to the second coupler (42). The second coupler (42) combines the signals and routes the combined signal to the RF-output port. The circuit arrangement enables the integration of the balanced amplifier and first and second couplers (26, 42) into a single power amplifier package to provide low power bypassing without the need of an external circulator component.
Abstract translation: 平衡功率放大器电路装置包括适于接收和放大信号的驱动放大器级（22）。 放大的信号被输入到第一耦合器（26）。 第一耦合器（26）产生同相信号和异相正交信号。 第一功率放大器（38）接收并放大同相信号。 第二功率放大器（40）接收并放大异相信号。 第一开关（28）将第一耦合器的隔离端口交替地连接到地（32）或旁路路径（36）。 第二耦合器（42）接收并组合放大的同相信号和放大的异相信号以产生组合信号。 第二开关（30）将第二耦合器（42）的隔离端口交替地连接到接地（34）或旁路路径（36）。 当功率放大器（38,40）断电时，第一耦合器（26）将RF信号分为同相信号和异相信号。 当功率放大器断电时，功率放大器（38,40）显示为信号的反射阻抗。 每个信号分别反射第一和第二功率放大器（38,40）。 第一耦合器（26）组合反射信号并将组合的信号通过旁通路径（36）传送到第二耦合器（42）。 第二耦合器（42）将信号分离成同相和异相信号，并将每个信号路由到功率放大器（38,40）。 功率放大器（38,40）将每个信号反射回第二耦合器（42）。 第二耦合器（42）组合信号并将组合信号路由到RF输出端口。 该电路装置能够将平衡放大器和第一和第二耦合器（26,42）集成到单个功率放大器封装中，以提供低功率旁路，而不需要外部循环器组件。
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公开(公告)号：WO2003055084A1
公开(公告)日：2003-07-03
申请号：PCT/US2002/033804
申请日：2002-10-16
Applicant: QUALCOMM, INCORPORATED
Inventor： CHAN, Paul, L. , KLAREN, Jonathan , PERSICO, Charles, J. , WALTER, Scott
IPC: H04B1/04
CPC classification number: H03F1/0261 , H03F1/32 , H03F2200/294 , H03F2200/372 , H04B1/0466
Abstract: Power detectors sense load mismatch conditions and cause the power output of a power amplifier to be reduced in response to a load mismatch. Transmitted and reflected power measurements are used to calculate a load mismatch criterion. A power amplifier is configured based on the calculated load mismatch criterion. A dual-directional coupler may be used to separate a power signal into transmitted and reflected components. With output power reduced under load mismatch conditions, signal distortion levels may be reduced to acceptable levels.
Abstract translation: 功率检测器检测负载失配条件，并且使功率放大器的功率输出响应于负载不匹配而减小。 传输和反射功率测量用于计算负载失配准则。 功率放大器基于计算出的负载失配准则进行配置。 双向耦合器可以用于将功率信号分离成传输和反射的部件。 在负载不匹配条件下输出功率降低时，信号失真电平可能会降低到可接受的水平。
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Patent Agency Ranking3.发明公开
公开(公告)号：EP3469683A1
公开(公告)日：2019-04-17
申请号：EP17726433.0
申请日：2017-05-17
Applicant: Qualcomm Incorporated
Inventor： TRUDEAU, Colby , WALTER, Scott , LOW, Zhen Ning , MAALOUF, Joseph Najib , GONG, Curtis , SHEVDE, Sumukh Ashok
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公开(公告)号：WO2019135871A1
公开(公告)日：2019-07-11
申请号：PCT/US2018/065210
申请日：2018-12-12
Applicant: QUALCOMM INCORPORATED
Inventor： FRANK, Wolfgang , GONG, Qizhi , WALTER, Scott , KAPOOR, Sanat
Abstract: Certain aspects of the present disclosure provide a circuit for dividing or combining power. The circuit generally includes a Wilkinson power divider, a first capacitive element, and a first resistive element coupled in parallel with the first capacitive element, wherein the first capacitive element and the first resistive element are coupled between a first port of the circuit and a first port of the Wilkinson power divider.
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5.发明申请DEVICES AND METHODS FOR CONTROLLING TRANSMITTER POWER SUPPLY BASED ON WIRELESS RECEIVER REQUEST 审中-公开基于无线接收器请求控制发射器电源的装置和方法
公开(公告)号：WO2017218132A1
公开(公告)日：2017-12-21
申请号：PCT/US2017/033151
申请日：2017-05-17
Applicant: QUALCOMM INCORPORATED
Inventor： TRUDEAU, Colby , WALTER, Scott , LOW, Zhen Ning , MAALOUF, Joseph Najib , GONG, Curtis , SHEVDE, Sumukh Ashok
Abstract: Devices and methods for controlling a power supply of a wireless power transmitter based on the request of a wireless power receiver are disclosed. One embodiment provides a wireless power receiver. The wireless power receiver includes a power receiver circuit configured to receive power from a wireless power transmitter at a level sufficient to power or charge a load. The wireless power receiver also includes a processor circuit configured to adjust a level of the received power being provided to the load based on a change in a level of received power to be requested to the wireless power transmitter. The processor circuit is further configured send to the wireless power transmitter the request to change the level of the received power to a first different level.
Abstract translation: 公开了用于基于无线电力接收器的请求来控制无线电力发射器的电力供应的设备和方法。 一个实施例提供无线电力接收器。 无线电力接收器包括电力接收器电路，该电力接收器电路被配置成以足以给负载供电或充电的水平从无线电力发射器接收电力。 该无线电力接收器还包括处理器电路，该处理器电路被配置为基于将被请求给无线电力发射器的接收电力的电平的变化来调整提供给负载的接收电力的电平。 处理器电路进一步被配置为向无线电力发射器发送将接收到的电力的等级改变为第一不同等级的请求。
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公开(公告)号：EP1442520A1
公开(公告)日：2004-08-04
申请号：EP02778684.7
申请日：2002-10-29
Applicant: Qualcomm Incorporated
Inventor： KLAREN, Jonathan , PERSICO, Charles, J. , WALTER, Scott , CHAN, Paul, L.
CPC classification number: H03F3/602 , H03F3/72 , H03F2200/198
Abstract: A balanced power amplifier circuit arrangement comprises a driver amplifier stage (22) adapted to receive and amplify a signal. The amplified signal is input to a first coupler (26). The first coupler (26) produces an in-phase signal and an out-of-phase quadrature signal. A first power amplifier (38) receives and amplifies the in-phase signal. A second power amplifier (40) receives and amplifies the out-of-phase signal. A first switch (28) alternately connects an isolated port of the first coupler to ground (32) or a bypass path (36). A second coupler (42) receives and combines the amplified in-phase signal and the amplified out-of-phase signal to produce a combined signal. A second switch (30) alternately connects an isolated port of the second coupler (42) to either ground (34) or the bypass path (36). When the power amplifiers (38, 40) are powered down, the first coupler (26) splits the RF-signal into an in-phase signal and an out-of-phase signal. The power amplifiers (38, 40) appear as reflective impedances to the signal when they are powered down. Each signal reflects off the first and second power amplifiers (38, 40), respectively. The first coupler (26) combines the reflected signals and routes the combined signal through the bypass path (36) to the second coupler (42). The second coupler (42) splits the signal into an in-phase and out-of-phase signal and routes each to the power amplifiers (38, 40). The power amplifiers (38, 40) reflect each signal back to the second coupler (42). The second coupler (42) combines the signals and routes the combined signal to the RF-output port. The circuit arrangement enables the integration of the balanced amplifier and first and second couplers (26, 42) into a single power amplifier package to provide low power bypassing without the need of an external circulator component.
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公开(公告)号：EP1442520B1
公开(公告)日：2010-07-21
申请号：EP02778684.7
申请日：2002-10-29
Applicant: QUALCOMM INCORPORATED
Inventor： KLAREN, Jonathan , PERSICO, Charles, J. , WALTER, Scott , CHAN, Paul, L.
CPC classification number: H03F3/602 , H03F3/72 , H03F2200/198
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