中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

48 records (took 0.024 seconds)

    MULTIBAND TRANSMITTER
    1.
    发明申请
    MULTIBAND TRANSMITTER 审中-公开

    公开(公告)号：WO2021168273A1

    公开(公告)日：2021-08-26

    申请号：PCT/US2021/018808

    申请日：2021-02-19

    Applicant: QUALCOMM INCORPORATED

    Inventor： LYN, Sean Joel ,  WANG, Cheng-Han ,  SONG, Hye Jin ,  LEE, Sang-Oh

    IPC: H04B1/00 ,  H03D7/14

    Abstract: Apparatuses and methods are disclosed regarding a multiband transmitter. In an example aspect, an apparatus for processing signals for wireless transmission includes a wireless interface device. The wireless interface device includes an upconverter, a tunable filter, and a driver amplifier. The upconverter has an output and is configured to upconvert a baseband frequency to a radio frequency based on a local oscillator signal. The tunable filter has an input and an output; the input of the tunable filter is coupled to the output of the upconverter. The driver amplifier has an input; the input of the driver amplifier is coupled to the output of the tunable filter.

    CLOCK SYNCHRONIZATION
    2.
    发明申请
    CLOCK SYNCHRONIZATION 审中-公开
    时钟同步

    公开(公告)号：WO2018057262A1

    公开(公告)日：2018-03-29

    申请号：PCT/US2017/049595

    申请日：2017-08-31

    Applicant: QUALCOMM INCORPORATED

    Inventor： BLACK, Justin ,  WANG, Cheng-Han ,  YANG, Jeongsik

    IPC: H03L7/14 ,  H04W52/02

    Abstract: An apparatus and a method are disclosed for synchronizing clock signals distributed within a wireless device. In some embodiments, a local oscillator (LO) clock signal is buffered and distributed to two or more transceivers within the wireless device. Each transceiver may include a configurable clock divider to divide the distributed LO clock signal and generate an output clock signal. A phase detector compares output clock signals from each of the configurable clock dividers and generates an output signal in accordance with a determined phase difference. The phase detector output signal may cause at least one of the configurable clock dividers to modify its respective output clock signal, and thereby synchronize output clock signals between different configurable clock dividers. In some embodiments, a clock signal from a configurable clock divider may be modified (shifted) by approximately 90 or 180 degrees.

    Abstract translation: 公开了一种用于同步分布在无线设备内的时钟信号的装置和方法。 在一些实施例中，本地振荡器（LO）时钟信号被缓冲并分配给无线设备内的两个或更多个收发机。 每个收发器可以包括可配置的时钟分频器以分配分布式LO时钟信号并生成输出时钟信号。 相位检测器比较来自每个可配置时钟分频器的输出时钟信号，并根据确定的相位差生成输出信号。 相位检测器输出信号可以使可配置时钟分频器中的至少一个修改其相应的输出时钟信号，从而使不同的可配置时钟分频器之间的输出时钟信号同步。 在一些实施例中，来自可配置时钟分频器的时钟信号可被修改（移位）大约90或180度。

    SIMULTANEOUS SIGNAL RECEIVER WITH INTERSPERSED FREQUENCY ALLOCATION
    4.
    发明申请
    SIMULTANEOUS SIGNAL RECEIVER WITH INTERSPERSED FREQUENCY ALLOCATION 审中-公开
    具有交互频率分配的同时信号接收

    公开(公告)号：WO2014138258A1

    公开(公告)日：2014-09-12

    申请号：PCT/US2014/020800

    申请日：2014-03-05

    Applicant: QUALCOMM INCORPORATED

    Inventor： KO, Jin-Su ,  KIM, Hong Sun ,  ZHAO, Liang ,  WANG, Cheng-Han ,  FARMER, Dominic Gerard

    IPC: H04B1/00

    CPC classification number: H04B1/16 ,  H04B1/005 ,  H04B1/0064 ,  H04B1/0075

    Abstract: Methods and circuits can down convert at least a first RF signal on a first path in a first frequency band to provide a first IF signal. A second RF signal on second path in a second frequency band can be down converted to provide a second IF signal. The first IF signal and the second IF signal are interspersed in the frequency domain, and the first frequency band is different from the second frequency band. A combiner can combine at least part of the first IF signal and the second IF signal to provide a combined signal on an output signal path for reception by a digital processing circuit. The first IF signal or second IF signal can be a Zero IF (ZIF), very low IF (VLIF), or Low IF (LIF) signal.

    Abstract translation: 方法和电路可以在第一频带中的第一路径上的至少第一RF信号下变频以提供第一IF信号。 在第二频带中的第二路径上的第二RF信号可被下变频以提供第二IF信号。 第一IF信号和第二IF信号分散在频域中，并且第一频带不同于第二频带。 组合器可以组合第一IF信号和第二IF信号的至少一部分，以在输出信号路径上提供组合信号以供数字处理电路接收。 第一IF信号或第二IF信号可以是零中频（ZIF），极低IF（VLIF）或低IF（LIF）信号。

    RECONFIGURABLE LNA FOR INCREASED JAMMER REJECTION
    6.
    发明申请
    RECONFIGURABLE LNA FOR INCREASED JAMMER REJECTION 审中-公开
    用于增加JAMMER拒绝的可重构LNA

    公开(公告)号：WO2014011299A1

    公开(公告)日：2014-01-16

    申请号：PCT/US2013/037241

    申请日：2013-04-18

    Applicant: QUALCOMM INCORPORATED

    Inventor： WANG, Cheng-Han ,  ZHAO, Liang ,  KIM, Hong Sun ,  KO, Jin-Su

    IPC: H03F3/193 ,  H03F1/56 ,  H03F3/45 ,  H04B1/10

    CPC classification number: H03F3/45188 ,  H03F1/565 ,  H03F3/193 ,  H03F2200/294 ,  H03F2200/546 ,  H03F2203/45386 ,  H03F2203/45641 ,  H03F2203/45726 ,  H04B1/109 ,  H04B1/3805

    Abstract: A reconfigurable LNA (104) for increased jammer rejection is disclosed. An exemplary embodiment includes an LNA (104) having a tunable resonant frequency, and a detector (132) configured to output a control signal to tune the resonant frequency of the LNA (104) to increase jammer suppression. An exemplary method includes detecting if a jammer is present, tuning a resonant frequency of an LNA (104) away from the jammer to increase jammer rejection if the jammer is present, and tuning the resonant frequency of the LNA (104) to a selected operating frequency if the jammer is not present.

    Abstract translation: 公开了一种用于增加干扰抑制的可重构LNA（104）。 示例性实施例包括具有可调谐谐振频率的LNA（104）和被配置为输出控制信号以调谐LNA（104）的谐振频率以增加干扰抑制的检测器（132）。 一种示例性方法包括检测干扰信号是否存在，如果干扰信号存在，则调谐LNA（104）的谐振频率远离干扰信号以增加干扰抑制，并且将LNA（104）的谐振频率调谐到所选择的操作 频率如果干扰不存在。

    TECHNIQUES FOR OPTIMIZING GAIN OR NOISE FIGURE OF AN RF RECEIVER
    7.
    发明申请
    TECHNIQUES FOR OPTIMIZING GAIN OR NOISE FIGURE OF AN RF RECEIVER 审中-公开
    用于优化RF接收机的增益或噪声的技术

    公开(公告)号：WO2011156503A1

    公开(公告)日：2011-12-15

    申请号：PCT/US2011/039650

    申请日：2011-06-08

    Applicant: QUALCOMM Incorporated ,  WANG, Cheng-Han

    Inventor： WANG, Cheng-Han

    IPC: H04B1/18

    CPC classification number: H04B1/18

    Abstract: Techniques for optimizing gain or noise figure of an RF receiver are disclosed. In an exemplary embodiment a controller controls a capacitor bank between an LNA and a mixer of the RF front end of the receiver. For a given center frequency a first set of capacitors is switched to the mixer and a second set of capacitors is switched to ground. The ratio of capacitance of the second set to the first set of capacitors affects either gain of the RF FE or noise figure of the receiver. Therefore, the RF FE of the receiver may be controlled in such a way as to optimize for either RF FE gain or for receiver noise figure.

    Abstract translation: 公开了用于优化RF接收机的增益或噪声系数的技术。 在示例性实施例中，控制器控制LNA与接收器的RF前端的混频器之间的电容器组。 对于给定的中心频率，第一组电容器被切换到混频器，并且第二组电容器被切换到地。 第二组电容与第一组电容器的电容比例影响接收机的RF FE或噪声系数的增益。 因此，接收机的RF FE可以以对于RF FE增益或接收机噪声系数优化的方式进行控制。

    DOUBLED BALANCED MIXER WITH IMPROVED COMPONENT MATCHING
    8.
    发明申请
    DOUBLED BALANCED MIXER WITH IMPROVED COMPONENT MATCHING 审中-公开
    双重平衡混合器与改进的组件匹配

    公开(公告)号：WO2011047354A1

    公开(公告)日：2011-04-21

    申请号：PCT/US2010/052966

    申请日：2010-10-15

    Applicant: QUALCOMM INCORPORATED ,  WANG, Cheng-Han

    Inventor： WANG, Cheng-Han

    IPC: H03D7/14

    CPC classification number: H03D7/1441 ,  H03D7/1458 ,  H03D7/1466 ,  H03D2200/0084

    Abstract: An improved active or passive double balanced mixer with reduced capacitor voltage mismatch is described. The double balanced mixer includes two sets of mixer circuits, each comprised of switches. Each switch is separately divided into a first portion and a second portion of unequal number of fingers. A first and second LO AC coupling capacitors associated with a given switch are coupled at one end to an LO signal. The outputs of the first LO AC coupling capacitors are coupled to the first portion of the first switch and the second portion of the second switch, respectively, while the outputs of the second LO AC coupling capacitors are coupled to the second portion of the first switch and the first portion of the second switch, respectively. In one embodiment, the unequal number of fingers is defined by an n-1 and an n+1 number of fingers, respectively. In an alternate embodiment, the mixer is an ADB mixer with a transconductance amplifier and two sets of mixer circuits as above.

    Abstract translation: 描述了具有降低的电容器电压失配的改进的有源或无源双平衡混频器。 双平衡混频器包括两组混频器电路，每组由开关组成。 每个开关被分成不同数目的手指的第一部分和第二部分。 与给定开关相关联的第一和第二LO AC耦合电容器在一端耦合到LO信号。 第一LO交流耦合电容器的输出分别耦合到第一开关的第一部分和第二开关的第二部分，而第二LO AC耦合电容器的输出耦合到第一开关的第二部分 和第二开关的第一部分。 在一个实施例中，不同数量的手指分别由n-1和n + 1个手指定义。 在替代实施例中，混频器是具有跨导放大器和如上所述的两组混频器电路的ADB混频器。

    CONCURRENT SUPPORT FOR MULTIPLE FREQUENCY BANDS FOR SATELLITE NAVIGATION SIGNALS
    9.
    发明申请
    CONCURRENT SUPPORT FOR MULTIPLE FREQUENCY BANDS FOR SATELLITE NAVIGATION SIGNALS 审中-公开

    公开(公告)号：WO2019212856A1

    公开(公告)日：2019-11-07

    申请号：PCT/US2019/029140

    申请日：2019-04-25

    Applicant: QUALCOMM INCORPORATED

    Inventor： ZENG, Yi ,  KIM, Hong Sun ,  WANG, Cheng-Han

    IPC: G01S19/32 ,  G01S19/21 ,  H03D7/16 ,  H04B1/00 ,  H04B1/30 ,  H04K3/00

    Abstract: A radio frequency (RF) receiver, for example a satellite positioning system receiver, can be configured to use a single phase locked loop for generating an oscillator signal to perform downconversion of signals in two different frequency bands using two or more local oscillators. A first RF signal portion includes a first signal band and undergoes double downconversion using a first mixer and a second mixer, while a second RF signal portion includes a second signal band and undergoes single downconversion using a single mixer. A controller is configured to determine a first oscillator divider value and a second oscillator divider value to avoid a jammer frequency and frequency dividers are used to generate the two or more local oscillators.

    A FULLY I/Q BALANCED QUADRATURE RADIO FREQUENCY MIXER WITH LOW NOISE AND LOW CONVERSION LOSS
    10.
    发明申请
    A FULLY I/Q BALANCED QUADRATURE RADIO FREQUENCY MIXER WITH LOW NOISE AND LOW CONVERSION LOSS 审中-公开
    完整的I / Q平衡低频无线电混频器，具有低噪声和低转换损耗

    公开(公告)号：WO2016130714A1

    公开(公告)日：2016-08-18

    申请号：PCT/US2016/017404

    申请日：2016-02-10

    Applicant: QUALCOMM INCORPORATED

    Inventor： WANG, Cheng-Han ,  CICALINI, Alberto ,  NGUYEN, Thinh Cat ,  VAHID FAR, Mohammad Bagher ,  RICHMOND, Jesse Aaron

    IPC: H03D7/14 ,  H03D7/16

    CPC classification number: H03D7/145 ,  H03D7/1433 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/1466 ,  H03D7/165 ,  H03D2200/0027

    Abstract: A method, an apparatus, and a system product for mixing radio frequency signals are provided. In one aspect, the apparatus is configured to perform switching of switches based on first, second, third, and fourth phased half duty clock signals. The apparatus convolves a differential input signal on a differential input port with the first, second, third, and fourth phased half duty cycle clock signals to concurrently generate a differential in-phase output signal and a differential quadrature-phase output signal on a dual differential output port. The first, second, third, and fourth phased half duty cycle clock signals are of the same frequency and out of phase by a multiple of ninety degrees with respect to each other.

    Abstract translation: 提供了一种用于混合射频信号的方法，装置和系统产品。 一方面，该装置被配置为基于第一，第二，第三和第四相位半占空时钟信号来执行开关的切换。 该装置利用第一，第二，第三和第四相位半占空比时钟信号在差分输入端口上卷积差分输入信号，以同时产生差分同相输出信号和双差分上的差分正交相输出信号 输出端口 第一，第二，第三和第四相位半占空比时钟信号的频率相同，相位相差90度。

Patent Agency Ranking