公开(公告)号：WO2016144570A1

公开(公告)日：2016-09-15

申请号：PCT/US2016/019745

申请日：2016-02-26

Applicant: QUALCOMM INCORPORATED

Inventor： YU, Guolei ,  WAN, Yicheng ,  SHI, Chunlei ,  MUKHERJEE, Sugato

IPC: H02M1/14 ,  H02M3/156 ,  H02M1/00

CPC classification number: H02M3/156 ,  H02M1/14 ,  H02M2001/0025 ,  H02M2001/0032 ,  Y02B70/16

Abstract: Disclosed is switching power supply that includes a pulse frequency modulation (PFM) mode of operation current feedback control. A reference current source is configured to output a reference current at one of several selectable levels. The level of the reference current may vary during operation of the current feedback control loop.

Abstract translation: 公开了包括脉冲频率调制（PFM）工作模式电流反馈控制的开关电源。 参考电流源被配置为以几个可选电平之一输出参考电流。 参考电流的电平可能在电流反馈控制环路的操作期间变化。

公开(公告)号：WO2017172345A1

公开(公告)日：2017-10-05

申请号：PCT/US2017/022197

申请日：2017-03-13

Applicant: QUALCOMM INCORPORATED

Inventor： KOSARAJU, Ajay Kumar ,  YU, Guolei ,  WAN, Yi-Cheng ,  MUKHERJEE, Sugato

IPC: H02M3/156

CPC classification number: H02M3/157 ,  G01R19/16571 ,  H02M1/08 ,  H02M3/1563 ,  H02M2001/0009 ,  H02M2001/0032 ,  Y02B70/16

Abstract: A duty cycle estimation circuit includes a latch circuit that receives a clock signal for a voltage regulator. The latch circuit outputs a duty cycle estimate. The duty cycle estimation circuit also includes a low pass filter coupled to an output of the latch circuit to receive the duty cycle estimate. The duty cycle estimation circuit further includes a comparator that receives, as input, an output of the low pass filter and a voltage regulator output. The comparator feeds back a feedback signal to the latch circuit.

Abstract translation: 占空比估计电路包括接收电压调节器的时钟信号的锁存电路。 锁存电路输出占空比估计。 占空比估计电路还包括耦合到锁存电路的输出以接收占空比估计的低通滤波器。 占空比估计电路还包括比较器，该比较器接收低通滤波器的输出和电压调节器输出作为输入。 比较器将反馈信号反馈给锁存电路。

公开(公告)号：WO2019212785A1

公开(公告)日：2019-11-07

申请号：PCT/US2019/028523

申请日：2019-04-22

Applicant: QUALCOMM INCORPORATED

Inventor： YU, Guolei ,  KOSARAJU, Ajay Kumar ,  KOSKI, Marko

IPC: H03K7/08 ,  H03K17/30 ,  H03K5/00

Abstract: An apparatus is disclosed that includes a voltage-controlled delay generator (136-1). The apparatus includes voltage-controlled timing circuitry (402), duty cycle detection circuitry (404), and output circuitry (406). The voltage-controlled timing circuitry is configured to receive a control voltage (216). The voltage-controlled timing circuitry includes a current source (410), a control transistor (412), and a capacitor (414) that are configured to produce a voltage indicator (526) based on the control voltage. The duty cycle detection circuitry is coupled to the voltage-controlled timing circuitry. The duty cycle detection circuitry is configured to detect the voltage indicator and provide a duty cycle indicator (528) based on the voltage indicator. The output circuitry is coupled to the duty cycle detection circuitry and is configured to generate a duty signal (208) based on the duty cycle indicator.