公开(公告)号：WO2012119123A2

公开(公告)日：2012-09-07

申请号：PCT/US2012/027603

申请日：2012-03-02

Applicant: QUALCOMM INCORPORATED ,  ZHANG, Gang

Inventor： ZHANG, Gang

IPC: H03L7/099

CPC classification number: H03L7/099 ,  H03L1/02 ,  H03L7/104

Abstract: The LC tank of a VCO includes a main varactor circuit and temperature compensation varactor circuit coupled in parallel with the main varactor circuit. The main varactor is used for fine tuning. The temperature compensation varactor circuit has a capacitance- voltage characteristic that differs from a capacitance-voltage characteristic of the main varactor circuit such that the effects of common mode noise across the two varactor circuits are minimized. The LC tank also has a plurality of switchable capacitor circuits provided for coarse tuning. To prevent breakdown of the main thin oxide switch in each of the switchable capacitor circuits, each switchable capacitor circuit has a capacitive voltage divider circuit that reduces the voltage across the main thin oxide switch when the main switch is off.

Abstract translation: VCO的LC箱包括与主变容二极管并联耦合的主变容二极管电路和温度补偿变容二极管电路。 主变容器用于微调。 温度补偿变容二极管的电容电压特性与主变容二极管电路的电容 - 电压特性不同，使两个变容二极管之间的共模噪声的影响最小化。 LC箱还具有用于粗调的多个可切换电容器电路。 为了防止每个可切换电容器电路中的主薄氧化物开关的破坏，每个可切换电容器电路具有电容分压器电路，当主开关断开时，电容分压电路降低主薄氧化物开关两端的电压。

公开(公告)号：WO2015038381A1

公开(公告)日：2015-03-19

申请号：PCT/US2014/053862

申请日：2014-09-03

Applicant: QUALCOMM INCORPORATED

Inventor： ZHANG, Gang ,  BOSSU, Frederic

IPC: H04B1/00

CPC classification number: H04L27/2647 ,  H04B1/005

Abstract: Certain aspects of the present disclosure provide methods and apparatus for generating local oscillator (LO) signals for multiple receive chains. One example circuit for generating first and second signals generally includes a first voltage controlled oscillator (VCO) configured to output the first signal at a first frequency and associated with a first receive chain for receiving a first carrier of an aggregated resource; and a second VCO configured to output the second signal at a second frequency and associated with a second receive chain for receiving a second carrier of the aggregated resource. The second frequency is different than the first frequency. In this manner, pulling or coupling between the two VCOs may be avoided, even if the two VCOs are implemented on the same radio frequency integrated circuit (RFIC).

Abstract translation: 本公开的某些方面提供了用于为多个接收链产生本地振荡器（LO）信号的方法和装置。 用于产生第一和第二信号的示例电路通常包括被配置为以第一频率输出第一信号并与第一接收链相关联的第一压控振荡器（VCO），用于接收聚合资源的第一载波; 以及第二VCO，被配置为以第二频率输出第二信号并与第二接收链相关联，用于接收聚合资源的第二载波。 第二频率与第一频率不同。 以这种方式，即使两个VCO实现在相同的射频集成电路（RFIC）上，也可以避免两个VCO之间的拉或耦合。

公开(公告)号：WO2010042764A1

公开(公告)日：2010-04-15

申请号：PCT/US2009/060063

申请日：2009-10-08

Applicant: QUALCOMM INCORPORATED ,  ZHANG, Gang

Inventor： ZHANG, Gang

IPC: H03K21/12

CPC classification number: H03L7/183 ,  H03K21/12 ,  H03L2207/50

Abstract: Design techniques for a low-power asynchronous counter. In an exemplary embodiment, the clock inputs and signal outputs of a plurality of flip-flops are serially concatenated to implement an asynchronous counting mechanism. The signal outputs of the plurality of flip-flops are sampled by successively delayed versions of a reference signal. Further design techniques for generating successively delayed versions of the reference signal are disclosed. In an exemplary embodiment, the asynchronous counting techniques may be utilized in a high-speed counter for a digital-phase locked loop (DPLL).

Abstract translation: 低功耗异步计数器的设计技术。 在示例性实施例中，多个触发器的时钟输入和信号输出串联连接以实现异步计数机制。 多个触发器的信号输出通过参考信号的连续延迟版本进行采样。 公开了用于产生参考信号的连续延迟版本的进一步的设计技术。 在示例性实施例中，可以在用于数字锁相环（DPLL）的高速计数器中使用异步计数技术。

公开(公告)号：WO2010017274A1

公开(公告)日：2010-02-11

申请号：PCT/US2009/052813

申请日：2009-08-05

Applicant: QUALCOMM INCORPORATED ,  ZHANG, Gang

Inventor： ZHANG, Gang

IPC: H03L7/085

CPC classification number: H03L7/085 ,  H03L7/1976 ,  H03L2207/50

Abstract: Techniques for converting an accumulated phase of a signal into a digital value in a digital phase-locked loop (DPLL). In an exemplary embodiment, a signal is coupled to a divide-by- N module that divides the frequency of the signal down by a divider ratio N. The divided signal is input to a delta phase-to-digital converter, which measures the phase difference between a rising edge of the divided signal and a rising edge of a reference signal. The accumulated divider ratios and the measured phase differences are combined to give an accumulated digital phase. Further techniques for varying the divider ratio N using a sigmato- delta modulator are disclosed.

Abstract translation: 用于将信号的累积相位转换为数字锁相环（DPLL）中的数字值的技术。 在示例性实施例中，信号被耦合到N分频模块，其将信号的频率下降除以分频比N.分频信号被输入到Δ相位数转换器，其测量相位 分频信号的上升沿与参考信号的上升沿之间的差。 累积的分频比和测量的相位差被组合以产生累积的数字相位。 公开了使用Sigmato-delta调制器改变分频比N的其它技术。

公开(公告)号：WO2009129258A1

公开(公告)日：2009-10-22

申请号：PCT/US2009/040555

申请日：2009-04-14

Applicant: QUALCOMM INCORPORATED ,  ZHANG, Gang ,  JAJOO, Abishek ,  HAN, Yiping

Inventor： ZHANG, Gang ,  JAJOO, Abishek ,  HAN, Yiping

IPC: H03L7/085

CPC classification number: H03L7/085 ,  H03L7/089 ,  H03L7/1976 ,  H03L2207/50

Abstract: A phase to digital converter, all digital phase locked loop, and apparatus having an all digital phase locked loop are described herein. The phase to digital converter includes a phase to frequency converter driving a time to digital converter. The time to digital converter determines a magnitude and sign of the phase differences output by the phase to frequency converter. The time to digital converter utilizes tapped delay lines and looped feedback counters to enable measurement of small timing differences typical of a loop tracking process and large timing differences typical of an loop acquisition process. The tapped delay lines permit the measurement of fractions of a reference period and enable lower power operation of the phase to digital converter by reducing requirements on the speed of the reference clock.

Abstract translation: 这里描述了一个相数转换器，全数字锁相环和具有全数字锁相环的装置。 相数转换器包括驱动时间到数字转换器的相位到频率转换器。 数字转换器的时间决定了相位变频器输出的相位差的大小和符号。 数字转换器的时间利用抽头延迟线和环路反馈计数器来测量环路跟踪过程中典型的小时序差异以及循环获取过程的典型时序差。 抽头延迟线允许测量参考周期的分数，并通过减少对参考时钟速度的要求，实现相位数字转换器的低功耗操作。

公开(公告)号：WO2009108815A1

公开(公告)日：2009-09-03

申请号：PCT/US2009/035349

申请日：2009-02-26

Applicant: QUALCOMM Incorporated ,  XU, Yang ,  ZHANG, Gang ,  GUDEM, Prasad S.

Inventor： XU, Yang ,  ZHANG, Gang ,  GUDEM, Prasad S.

IPC: H03L7/197

CPC classification number: H03L7/1974

Abstract: The clock signal supplied to the delta-sigma modulator in a fractional-N phase-locked loop is dithered. In one example, the PLL includes a novel programmable clock dithering circuit. The programmable clock dithering circuit is controllable via a serial bus to dither the phase of the clock signal in a selected one of several ways. If the clock signal is dithered in a first way (pseudo-random phase dithering), then the power of digital noise generated by the delta-sigma modulator is spread over a frequency band, thereby reducing the degree to which the noise interferes with other circuitry. If the clock signal is dithered in a second way (rotational phase dithering), then the power of digital noise is frequency shifted such that the degree to which the noise interferes with the other circuitry is reduced. The programmable clock dithering circuit can be controlled in other ways. For example, dithering can be programmably disabled.

Abstract translation: 在分数N锁相环中提供给Δ-Σ调制器的时钟信号被抖动。 在一个示例中，PLL包括新颖的可编程时钟抖动电路。 可编程时钟抖动电路可通过串行总线进行控制，以选择的几种方式对时钟信号的相位进行抖动。 如果时钟信号以第一种方式抖动（伪随机相位抖动），则由Δ-Σ调制器产生的数字噪声的功率在频带上扩展，从而降低噪声干扰其他电路的程度 。 如果时钟信号以第二种方式抖动（旋转相位抖动），则数字噪声的功率被频移，使得噪声干扰另一电路的程度降低。 可编程时钟抖动电路可以以其他方式进行控制。 例如，抖动可以可编程地禁用。

公开(公告)号：WO2009088789A1

公开(公告)日：2009-07-16

申请号：PCT/US2008/088262

申请日：2008-12-24

Applicant: QUALCOMM Incorporated ,  ZHANG, Gang

Inventor： ZHANG, Gang

IPC: H03L7/085 ,  H03L7/093 ,  H03L7/099 ,  H03L7/197

CPC classification number: H03L7/085 ,  H03L7/093 ,  H03L7/0991 ,  H03L7/1976 ,  H03L2207/50

Abstract: A phase-locked loop includes a phase-to-digital converter portion as well as a novel correction portion. The phase-to-digital converter (PDC) portion outputs a stream of first phase error words. The novel correction portion receives the first phase error words and generates a stream of second phase error words that is supplied to a loop filter. The PDC portion has a phase-to-digital transfer function that exhibits certain imperfections. In a first example, the correction portion determines an average difference between pairs of first phase error words, and uses this average difference to normalize the first phase error words to correct for changes in PDC portion transfer function slope due to changes in delay element propagation delay. In a second example, the correction portion corrects for gain mismatches in PDC portion transfer function. In a third example, the correction portion corrects for offset mismatches in PDC portion transfer function.

Abstract translation: 锁相环包括相数转换器部分以及新颖的校正部分。 相位数转换器（PDC）部分输出第一相位误差字的流。 新颖的校正部分接收第一相位误差字，并产生提供给环路滤波器的第二相位误差字的流。 PDC部分具有展现某些缺陷的相位数转换功能。 在第一示例中，校正部分确定第一相位误差字对之间的平均差，并且使用该平均差来归一化第一相位误差字，以校正由于延迟元件传播延迟的变化导致的PDC部分传递函数斜率的变化 。 在第二示例中，校正部分校正PDC部分传递函数中的增益失配。 在第三示例中，校正部分校正PDC部分传递函数中的偏移不匹配。

公开(公告)号：WO2008005677A1

公开(公告)日：2008-01-10

申请号：PCT/US2007/071407

申请日：2007-06-15

Applicant: QUALCOMM Incorporated ,  ZHANG, Gang

Inventor： ZHANG, Gang

IPC: H03L7/093 ,  H03H11/12

CPC classification number: H03L7/093 ,  H03H7/06 ,  H03H11/126 ,  H03L7/0893 ,  H03L2207/06

Abstract: A loop filter with noise cancellation includes first and second signal paths (720, 730), an operational amplifier (op-amp) (736), and a noise cancellation path. (740) The first signal path (720)provides a first transfer function (e.g., a lowpass response) for a first signal. The second signal path (730)provides a second transfer function (e.g., an integration response) for a second signal. The second signal is a scaled version of, and smaller than, the first signal by a factor of alpha, where alpha is greater than one. A capacitor (734) in the second signal path may be scaled smaller by a factor of alpha. The op-amp couples to the first and second signal paths and facilitates summing of signals from the first and second signal paths to generate a control signal (VCTRL) having op-amp noise. The noise cancellation path (740) couples to the op-amp and provides a noise cancellation signal (VCTRL) used to cancel the op-amp noise in the control signal. The control signal (VCTRL) and the noice cancelled signal (VN) may be applied to respective nodes of a varicap(750) included in a voltage controlled oscillator (VCO) so as to improve phase noice of the VCO.

Abstract translation: 具有噪声消除的环路滤波器包括第一和第二信号路径（720,730），运算放大器（运算放大器）（736）和噪声消除路径。 （740）第一信号路径（720）为第一信号提供第一传递函数（例如，低通响应）。 第二信号路径（730）为第二信号提供第二传递函数（例如，积分响应）。 第二信号是第一信号的缩放版本，并且小于第一信号乘以α的因子，其中α大于1。 第二信号路径中的电容器（734）可以按比例缩小α的因子。 运算放大器耦合到第一和第二信号路径，并且有助于来自第一和第二信号路径的信号的相加，以产生具有运算放大器噪声的控制信号（VCTRL）。 噪声消除路径（740）耦合到运算放大器并且提供用于消除控制信号中的运算放大器噪声的噪声消除信号（VCTRL）。 控制信号（VCTRL）和噪声消除信号（VN）可以被施加到包括在压控振荡器（VCO）中的变容二极管（750）的相应节点，以便改善VCO的相位噪声。

公开(公告)号：WO2015183588A1

公开(公告)日：2015-12-03

申请号：PCT/US2015/030948

申请日：2015-05-15

Applicant: QUALCOMM INCORPORATED

Inventor： LO, Yung-Chung ,  ZHANG, Gang ,  HAN, Yiping ,  BOSSU, Frederic ,  HUNG, Tsai-Pi ,  CHANG, Jae-Hong

IPC: G05F1/575

CPC classification number: H02M3/156 ,  G05F1/575 ,  H02M1/00 ,  H02M2001/0077

Abstract: A method, an apparatus, and a computer program product are provided. The apparatus may be a regulator circuit. The regulator circuit includes a first voltage regulator to regulate a first input voltage to the first voltage regulator, the first voltage regulator including a P-type metal-oxide-semiconductor (PMOS), and a second voltage regulator to regulate a second input voltage to the second voltage regulator, the second voltage regulator including an N-type metal-oxide-semiconductor (NMOS). In an aspect, the first voltage regulator is coupled to the second voltage regulator.

Abstract translation: 提供了一种方法，装置和计算机程序产品。 该装置可以是调节器电路。 调节器电路包括第一电压调节器，用于调节到第一电压调节器的第一输入电压，第一电压调节器包括P型金属氧化物半导体（PMOS）和第二电压调节器，以将第二输入电压调节到 第二电压调节器，第二电压调节器包括N型金属氧化物半导体（NMOS）。 在一方面，第一电压调节器耦合到第二电压调节器。

公开(公告)号：WO2015183584A1

公开(公告)日：2015-12-03

申请号：PCT/US2015/030883

申请日：2015-05-14

Applicant: QUALCOMM INCORPORATED

Inventor： PAI, Hung-Chuan ,  ZHANG, Gang

IPC: H03L7/16 ,  H03L7/081 ,  H03K5/00 ,  H03K5/13

CPC classification number: H03K21/02 ,  H03K5/00006 ,  H03K5/133 ,  H03K23/667 ,  H03L7/081 ,  H03L7/16 ,  H04B1/40

Abstract: Aspects of a reconfigurable frequency divider circuit are provided. A reconfigurable frequency divider can include a frequency divider that is configured to receive an input signal. The frequency divider can also include a delay circuit that is configured to receive a divided signal produced by the frequency divider. The frequency divider can also include a frequency multiplier that is configured to produce an output signal based on the delayed signal produced by the delay circuit, wherein the delay circuit is configured to receive the output signal.

Abstract translation: 提供可重构分频器电路的方面。 可重构分频器可以包括被配置为接收输入信号的分频器。 分频器还可以包括被配置为接收由分频器产生的分频信号的延迟电路。 分频器还可以包括被配置为基于由延迟电路产生的延迟信号产生输出信号的倍频器，其中延迟电路被配置为接收输出信号。