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    TUNING VOLTAGE RANGE EXTENSION CIRCUIT AND METHOD
    1.
    发明申请
    TUNING VOLTAGE RANGE EXTENSION CIRCUIT AND METHOD 审中-公开
    调谐电压范围扩展电路及方法

    公开(公告)号：WO2013071274A1

    公开(公告)日：2013-05-16

    申请号：PCT/US2012/064731

    申请日：2012-11-12

    Applicant: QUALCOMM INCORPORATED

    Inventor： NAVUBOTHU, Swarna L. ,  ZHONG, Cheng ,  DANG, Nam V. ,  KONG, Xiaohua

    IPC: H03L7/099 ,  H03K3/03

    CPC classification number: H03L7/0995 ,  H03K3/0315

    Abstract: A circuit includes a first path including a first transistor and a first current source. The first transistor is responsive to a tuning voltage. The circuit also includes a tuning voltage range extension circuit responsive to the tuning voltage. The tuning voltage range extension circuit is configured to selectively change current supplied by the first path as the tuning voltage exceeds a capacity threshold of the first transistor.

    Abstract translation: 电路包括包括第一晶体管和第一电流源的第一路径。 第一晶体管响应调谐电压。 电路还包括响应于调谐电压的调谐电压范围扩展电路。 调谐电压范围扩展电路被配置为当调谐电压超过第一晶体管的容量阈值时选择性地改变由第一路径提供的电流。

    MEMORY BIT LINE LEAKAGE REPAIR
    3.
    发明申请
    MEMORY BIT LINE LEAKAGE REPAIR 审中-公开
    存储位线泄漏维修

    公开(公告)号：WO2004097842A1

    公开(公告)日：2004-11-11

    申请号：PCT/US2003/033358

    申请日：2003-10-20

    Applicant: QUALCOMM, INCORPORATED

    Inventor： CHEN, Nan ,  ZHONG, Cheng ,  SANI, Mehdi Hamidi

    IPC: G11C29/00

    CPC classification number: G11C29/025 ,  G11C11/41 ,  G11C29/02 ,  G11C2029/1204 ,  G11C2029/5006

    Abstract: Techniques for replacing and eliminating paths causing channel leakage current. In one embodiment, one or more precharge enable transistors and a precharge enable signal are added to a circuit configuration. The precharge enable transistors are designed to remain on and simply pass a signal in a properly functioning path. When a leakage path is identified, such as during IDDQ testing, the precharge enable signal is set to turn off the precharge enable transistors. When the precharge enable transistors are off, the leakage path is disrupted, and the leakage current stopped. The path may be replaced with a redundant path.

    Abstract translation: 用于替代和消除引起通道泄漏电流的路径的技术。 在一个实施例中，将一个或多个预充电使能晶体管和预充电使能信号加到电路配置中。 预充电使能晶体管被设计为保持在正常功能的路径上并简单地传递信号。 当识别泄漏路径时，例如在IDDQ测试期间，预充电使能信号被设置为关闭预充电使能晶体管。 当预充电使能晶体管截止时，泄漏路径被破坏，并且泄漏电流停止。 可以用冗余路径替换路径。

    LEAKAGE CURRENT REDUCTION FOR CMOS MEMORY CIRCUITS
    4.
    发明申请
    LEAKAGE CURRENT REDUCTION FOR CMOS MEMORY CIRCUITS 审中-公开
    CMOS存储器电路的漏电流减少

    公开(公告)号：WO2004090907A1

    公开(公告)日：2004-10-21

    申请号：PCT/US2004/010308

    申请日：2004-04-02

    Applicant: QUALCOMM INCORPORATED ,  CHEN, Nan ,  ZHONG, Cheng ,  SANI, Mehdi Hamidi

    Inventor： CHEN, Nan ,  ZHONG, Cheng ,  SANI, Mehdi Hamidi

    IPC: G11C11/412

    CPC classification number: G11C11/4074 ,  G11C11/413 ,  G11C2207/2227

    Abstract: A CMOS integrated circuit (e.g., an SRAM or a DRAM) is partitioned into a core block, a peripheral block, and a retention block. The core block includes circuits (e.g., memory cells) that are powered on at all times and is coupled directly to power supply and circuit ground. The peripheral block includes circuits that may be powered on or off and are coupled to the power supply via a head switch and/or to circuit ground via a foot switch. The switches and the core block may be implemented with high threshold voltage (high-Vt) FET devices to reduce leakage current. The peripheral block may be implemented with low-Vt FET devices for high-speed operation. The retention block includes circuits (e.g., pull-up devices) that maintain signal lines (e.g., word lines) at a predetermined level so that the internal states of the core block are retained when the peripheral block is powered off.

    Abstract translation: CMOS集成电路（例如，SRAM或DRAM）被划分为核心块，外围块和保留块。 核心块包括始终上电并直接耦合到电源和电路接地的电路（例如，存储器单元）。 外围块包括可以通电或断开的电路，并且经由头开关和/或经由脚踏开关电路接地到电源。 开关和核心块可以用高阈值电压（高Vt）FET器件实现，以减少漏电流。 外围块可以用用于高速操作的低Vt FET器件来实现。 保持块包括将信号线（例如，字线）保持在预定水平的电路（例如，上拉装置），使得当外围块被断电时，核心块的内部状态被保持。

    MRAM DEVICE WITH SHARED SOURCE LINE
    6.
    发明申请
    MRAM DEVICE WITH SHARED SOURCE LINE 审中-公开
    具有共享源线的MRAM器件

    公开(公告)号：WO2009079660A1

    公开(公告)日：2009-06-25

    申请号：PCT/US2008/087741

    申请日：2008-12-19

    Applicant: QUALCOMM Incorporated ,  YOON, Sei, Seung ,  ZHONG, Cheng ,  PARK, Dongkyu ,  ABU-RAHMA, Mohamed, H.

    Inventor： YOON, Sei, Seung ,  ZHONG, Cheng ,  PARK, Dongkyu ,  ABU-RAHMA, Mohamed, H.

    IPC: G11C11/16

    CPC classification number: G11C11/1675 ,  G11C11/1659 ,  G11C11/1673

    Abstract: In a particular embodiment, a memory device includes a first memory cell and a second memory cell. The memory device also includes a first bit line associated with the first memory cell and a second bit line associated with the second memory cell. The memory device also includes a source line coupled to the first memory cell and coupled to the second memory cell. The memory cell may be formed by spin transfer torque magnetoresistive memory cells having selection field effect transistors. The memory cell may also be formed as complementary cell pairs. Half-selected cells are supplied with or across them to prevent read disturb.

    Abstract translation: 在特定实施例中，存储器设备包括第一存储器单元和第二存储器单元。 存储器件还包括与第一存储器单元相关联的第一位线和与第二存储器单元相关联的第二位线。 存储器件还包括耦合到第一存储器单元并耦合到第二存储器单元的源极线。 存储单元可以由具有选择场效应晶体管的自旋转移转矩磁阻存储单元形成。 存储单元也可以形成为互补单元对。 半选择的单元格提供或跨越它们以防止读取干扰。

    AN APPARATUS TO IMPLEMENT SYMMETRIC SINGLE-ENDED TERMINATION IN DIFFERENTIAL VOLTAGE-MODE DRIVERS
    7.
    发明申请
    AN APPARATUS TO IMPLEMENT SYMMETRIC SINGLE-ENDED TERMINATION IN DIFFERENTIAL VOLTAGE-MODE DRIVERS 审中-公开
    在差分电压模式驱动器中实现对称单端终止的设备

    公开(公告)号：WO2013049757A1

    公开(公告)日：2013-04-04

    申请号：PCT/US2012/058172

    申请日：2012-09-30

    Applicant: QUALCOMM INCORPORATED ,  ZHONG, Cheng ,  DANG, Vannam ,  LI, Miao ,  MAAROUF, Fares K. ,  SOWLATI, Tirdad

    Inventor： ZHONG, Cheng ,  DANG, Vannam ,  LI, Miao ,  MAAROUF, Fares K. ,  SOWLATI, Tirdad

    IPC: H04L25/02 ,  H03K19/0185

    CPC classification number: H04L25/0274 ,  H04L25/0278

    Abstract: A differential voltage mode driver for implementing symmetric single ended termination includes an output driver circuitry having a predefined termination impedance. The differential voltage mode driver also includes an output driver replica having independently controlled first and second portions. The first and second portions are independently controlled to establish a substantially equal on-resistance of the first and the second portions. The output driver replica controls the predefined termination impedance of the output driver circuitry.

    Abstract translation: 用于实现对称单端终端的差分电压模式驱动器包括具有预定义的终端阻抗的输出驱动器电路。 差分电压模式驱动器还包括具有独立控制的第一和第二部分的输出驱动器副本。 独立地控制第一和第二部分以建立第一和第二部分的基本相等的导通电阻。 输出驱动器副本控制输出驱动器电路的预定终止阻抗。

    HIGH SPEED DATA TESTING WITHOUT HIGH SPEED BIT CLOCK
    9.
    发明申请
    HIGH SPEED DATA TESTING WITHOUT HIGH SPEED BIT CLOCK 审中-公开
    高速数据测试无高速位时钟

    公开(公告)号：WO2013016466A1

    公开(公告)日：2013-01-31

    申请号：PCT/US2012/048207

    申请日：2012-07-25

    Applicant: QUALCOMM INCORPORATED ,  LI, Miao ,  KONG, Xiaohua ,  DANG, Nam V. ,  ZHONG, Cheng

    Inventor： LI, Miao ,  KONG, Xiaohua ,  DANG, Nam V. ,  ZHONG, Cheng

    IPC: G09G5/00 ,  H04L1/00 ,  H04L1/20 ,  H04N5/00

    CPC classification number: G01R31/3177 ,  G06F1/04 ,  G09G5/006 ,  G09G2350/00 ,  G09G2370/12

    Abstract: System and method for testing a high speed data path without generating a high speed bit clock, includes selecting a first high speed data path from a plurality of data paths for testing. Coherent clock data patterns are driven on one or more of remaining data paths of the plurality of data paths, wherein the coherent clock data patterns are in coherence with a low speed base clock. The first high speed data path is sampled by the coherent clock data patterns to generate a sampled first high speed data path, which is then tested at a speed of the low speed base clock.

    Abstract translation: 用于测试高速数据路径而不产生高速位时钟的系统和方法包括从多个数据路径中选择第一高速数据路径进行测试。 在多个数据路径中的一个或多个剩余数据路径上驱动相干时钟数据模式，其中相干时钟数据模式与低速基准时钟保持一致。 第一高速数据路径被相干时钟数据模式采样，以产生采样的第一高速数据路径，然后以低速基准时钟的速度进行测试。

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