公开(公告)号：US11789769B2

公开(公告)日：2023-10-17

申请号：US16791361

申请日：2020-02-14

Applicant: QUALCOMM TECHNOLOGIES, INC.

Inventor： Muthu M. Baskaran ,  Thomas Henretty ,  M. H. Langston ,  Richard A. Lethin ,  Benoit J. Meister ,  Nicolas T. Vasilache ,  David E. Wohlford

IPC: G06F9/46 ,  G06F9/48

CPC classification number: G06F9/4843

Abstract: In a system for automatic generation of event-driven, tuple-space based programs from a sequential specification, a hierarchical mapping solution can target different runtimes relying on event-driven tasks (EDTs). The solution uses loop types to encode short, transitive relations among EDTs that can be evaluated efficiently at runtime. Specifically, permutable loops translate immediately into conservative point-to-point synchronizations of distance one. A runtime-agnostic which can be used to target the transformed code to different runtimes.

公开(公告)号：US11520856B2

公开(公告)日：2022-12-06

申请号：US17086772

申请日：2020-11-02

Applicant: QUALCOMM TECHNOLOGIES, INC.

Inventor： Muthu M. Baskaran ,  David Bruns-Smith ,  James Ezick ,  Richard A. Lethin

IPC: G06F17/16

Abstract: A system for performing tensor decomposition in a selective expansive and/or recursive manner, a tensor is decomposed into a specified number of components, and one or more tensor components are selected for further decomposition. For each selected component, the significant elements thereof are identified, and using the indices of the significant elements a sub-tensor is formed. In a subsequent iteration, each sub-tensor is decomposed into a respective specified number of components. Additional sub-tensors corresponding to the components generated in the subsequent iteration are formed, and these additional sub-tensors may be decomposed further in yet another iteration, until no additional components are selected. The mode of a sub-tensor can be decreased or increased prior to decomposition thereof. Components likely to reveal information about the data stored in the tensor can be selected for decomposition.

公开(公告)号：US11726197B2

公开(公告)日：2023-08-15

申请号：US16653201

申请日：2019-10-15

Applicant: QUALCOMM TECHNOLOGIES, INC.

Inventor： Muthu M. Baskaran ,  Thomas Henretty ,  Ann Johnson ,  Athanasios Konstantinidis ,  M. H. Langston ,  Janice O. McMahon ,  Benoit J. Meister ,  Paul D. Mountcastle ,  Aale Naqvi ,  Benoit Pradelle ,  Tahina Ramananandro ,  Sanket Tavarageri ,  Richard A. Lethin

IPC: G01S13/72 ,  G01S7/41 ,  G01S7/48 ,  B64C39/02 ,  G01S3/786 ,  G01S17/66 ,  B64U101/20

CPC classification number: G01S13/723 ,  G01S7/411 ,  G01S7/4802 ,  B64C39/024 ,  B64U2101/20 ,  G01S3/7864 ,  G01S7/4808 ,  G01S17/66

Abstract: A system for determining the physical path of an object can map several candidate paths to a suitable path space that can be explored using a convex optimization technique. The optimization technique may take advantage of the typical sparsity of the path space and can identify a likely physical path using a function of sensor observation as constraints. A track of an object can also be determined using a track model and a convex optimization technique.

公开(公告)号：US11567746B2

公开(公告)日：2023-01-31

申请号：US16927016

申请日：2020-07-13

Applicant: QUALCOMM TECHNOLOGIES, INC.

Inventor： Muthu M. Baskaran ,  Thomas Henretty ,  Richard A. Lethin ,  Benoit J. Meister

IPC: G06F8/41

Abstract: In a sequence of major computational steps or in an iterative computation, a stencil amplifier can increase the number of data elements accessed from one or more data structures in a single major step or iteration, thereby decreasing the total number of computations and/or communication operations in the overall sequence or the iterative computation. Stencil amplification, which can be optimized according to a specified parameter such as compile time, rune time, code size, etc., can improve the performance of a computing system executing the sequence or the iterative computation in terms of run time, memory load, energy consumption, etc. The stencil amplifier typically determines boundaries, to avoid erroneously accessing data elements not present in the one or more data structures.

公开(公告)号：US11500557B2

公开(公告)日：2022-11-15

申请号：US16745890

申请日：2020-01-17

Applicant: QUALCOMM TECHNOLOGIES, INC.

Inventor： Muthu M. Baskaran ,  Thomas Henretty ,  Ann Johnson ,  Athanasios Konstantinidis ,  M. H. Langston ,  Janice O. McMahon ,  Benoit J. Meister ,  Paul D. Mountcastle ,  Aale Naqvi ,  Benoit Pradelle ,  Tahina Ramananandro ,  Sanket Tavarageri ,  Richard A. Lethin

IPC: G06F9/44 ,  G06F3/06 ,  G06F8/41

Abstract: A compilation system using an energy model based on a set of generic and practical hardware and software parameters is presented. The model can represent the major trends in energy consumption spanning potential hardware configurations using only parameters available at compilation time. Experimental verification indicates that the model is nimble yet sufficiently precise, allowing efficient selection of one or more parameters of a target computing system so as to minimize power/energy consumption of a program while achieving other performance related goals. A voltage and/or frequency optimization and selection is presented which can determine an efficient dynamic hardware configuration schedule at compilation time. In various embodiments, the configuration schedule is chosen based on its predicted effect on energy consumption. A concurrency throttling technique based on the energy model can exploit the power-gating features exposed by the target computing system to increase the energy efficiency of programs.