公开(公告)号：US20190141840A1

公开(公告)日：2019-05-09

申请号：US16051772

申请日：2018-08-01

Applicant: R&D Circuits, Inc.

Inventor： Donald Eric Thompson ,  Dhananjaya Turpuseema

IPC: H05K3/42 ,  H05K3/46 ,  H05K1/11

Abstract: A method and structure that forms a PCB while removing or eliminating a stub from a via without back-drilling or doing multi-laminations. In the preferred embodiment, the printed circuit board includes a via extending through a plurality of stacked layers. The via includes a plated through hole that is connected to at least two other metalized layers. There is a portion of the via that is extraneous and that has a negative performance on the functionality of the printed circuit board. The single lamination buried via method adds a seed layer resist that prevents an electrical connection during electroplating thus preventing the via from metalizing where it is not desired.