公开(公告)号：WO2015153122A1

公开(公告)日：2015-10-08

申请号：PCT/US2015/021225

申请日：2015-03-18

Applicant: RAYTHEON COMPANY

Inventor： VAMPOLA, John, L. ,  HARRIS, Micky, R. ,  KEAN, Bryan, W. ,  BOTTS, Steven, E.

IPC: H04N5/367 ,  H04N5/378 ,  H04N17/00

CPC classification number: H04N5/3745 ,  H01L27/14643 ,  H04N5/367 ,  H04N5/3765 ,  H04N5/378 ,  H04N17/002

Abstract: A focal plane array having: an imaging array section, comprising: an array of electromagnetic radiation detectors; and an address section providing outputs from selectively enabled detectors. The imaging array section comprises a plurality of circuit blocks, each one of the circuit blocks having a primary circuit and a redundant circuit. Test circuitry is provided for supplying test signals to test each one of the primary circuits and determining whether a response from the test signals is proper or improper and for storing in the test circuitry in response to such determining select signals associated with each one of the tested circuit blocks. An array controller is provided for, during a subsequent normal operating mode, providing timing pulses to the address section wherein the address section selectively enables the detectors using either the primary or redundant circuits in the plurality of circuit blocks selectively in accordance with the stored select signals.

Abstract translation: 1.一种焦平面阵列，具有：成像阵列部，包括：电磁辐射检测器阵列; 以及提供来自选择性启用的检测器的输出的地址部分。 成像阵列部分包括多个电路块，每个电路块具有主电路和冗余电路。 提供测试电路用于提供测试信号以测试主电路中的每一个，并且确定来自测试信号的响应是否适当或不正确，并且响应于与测试的每一个相关联的这样的确定选择信号来存储在测试电路中 电路块。 提供阵列控制器，用于在随后的正常操作模式期间向地址部分提供定时脉冲，其中地址段根据所存储的选择信号有选择地使能多个电路块中的主电路或冗余电路的检测器 。

公开(公告)号：WO2015084631A1

公开(公告)日：2015-06-11

申请号：PCT/US2014/067278

申请日：2014-11-25

Applicant: RAYTHEON COMPANY

Inventor： BOTTS, Steven, E. ,  HARRIS, Micky, R. ,  VAMPOLA, John, L. ,  MCLAUGHLIN, Michael

IPC: H01L27/146 ,  H04N5/33 ,  H04N5/341 ,  H04N5/3745

CPC classification number: H04N5/23229 ,  G06K9/46 ,  G06K2009/4666 ,  H04N5/332 ,  H04N5/341 ,  H04N5/369 ,  H04N5/37452

Abstract: A focal plane array having: a plurality of detectors; a plurality of unit cell sections, each section being fed by charge produced by corresponding detector for producing a sequence of frames; and a plurality of sets of storage sections, each section being coupled to a corresponding one of the unit cells. Each set of storage sections includes a plurality of storage units for sequentially storing the frames. A region of interest selector section examines the frames of the plurality of unit cells, to detect at least one of the frames having a predetermined characteristic. A processor: (i) identifies a sub-set of the plurality of unit cells proximate the detected unit cells having the predetermined characteristic to establish a region of interest; and (ii) sequentially reads the plurality of storage units in the storage sections coupled to the sub-set of unit cells in the established region of interest.

Abstract translation: 一种焦平面阵列，具有：多个检测器; 多个单元单元部分，每个部分由相应的检测器产生的电荷馈送以产生一系列帧; 以及多个存储部分组，每个部分耦合到相应的一个单位单元。 每组存储部分包括用于顺序存储帧的多个存储单元。 感兴趣区域选择器部分检查多个单位单元的帧，以检测具有预定特性的帧中的至少一个。 一种处理器：（i）识别靠近具有预定特征的检测单位单元的多个单位单元的子集，以建立感兴趣的区域; 以及（ii）顺序地读取在所建立的感兴趣区域中耦合到单位单元子集的存储部分中的多个存储单元。

公开(公告)号：WO2011142899A1

公开(公告)日：2011-11-17

申请号：PCT/US2011/030691

申请日：2011-03-31

Applicant: RAYTHEON COMPANY ,  HARRIS, Micky, R. ,  SHIN, Jeong-gyun

Inventor： HARRIS, Micky, R. ,  SHIN, Jeong-gyun

IPC: H01L23/544

CPC classification number: G06F17/505

Abstract: Methods and systems for digitally decoding integrated circuit blocks are provided. A method for decoding integrated circuit blocks may include providing a previous block output and an increment value input to a first identification block of a first integrated circuit block, providing the output of the first identification t block and the increment value input to one of a plurality of intermediate identification blocks, and providing an output of the last of the plurality of intermediate identification blocks and the increment value input to a last identification block, wherein the output of the last identification block is indicative of the number of integrated circuit blocks.

Abstract translation: 提供了用于数字解码集成电路块的方法和系统。 用于解码集成电路块的方法可以包括提供先前块输出和输入到第一集成电路块的第一标识块的增量值，提供第一标识t块的输出和输入到多个 并且提供多个中间标识块中的最后一个的输出和输入到最后的识别块的增量值，其中最后的识别块的输出指示集成电路块的数量。

公开(公告)号：WO2010083078A1

公开(公告)日：2010-07-22

申请号：PCT/US2010/020288

申请日：2010-01-07

Applicant: RAYTHEON COMPANY ,  VAMPOLA, John, L. ,  HARRIS, Micky, R.

Inventor： VAMPOLA, John, L. ,  HARRIS, Micky, R.

IPC: H01L27/146

CPC classification number: H01L27/14643 ,  H01L27/14609

Abstract: A unit cell includes a MOSFET and an integration capacitor. The MOSFET includes a source, a drain, and a gate. The drain is coupled to the source, and the MOSFET is operable to store a first portion of an electric charge corresponding to a detected light intensity. The integration capacitor includes a first end and a second end. The first end is coupled to the drain of the MOSFET and the second end is coupled to a ground. The integration capacitor is operable to store a second portion of the electric charge corresponding to the detected light intensity.

Abstract translation: 单元电池包括MOSFET和积分电容器。 MOSFET包括源极，漏极和栅极。 漏极耦合到源极，并且MOSFET可操作地存储对应于检测到的光强度的电荷的第一部分。 积分电容器包括第一端和第二端。 第一端耦合到MOSFET的漏极，第二端耦合到地。 积分电容器可操作地存储对应于检测到的光强度的电荷的第二部分。

公开(公告)号：WO2015116493A1

公开(公告)日：2015-08-06

申请号：PCT/US2015/012655

申请日：2015-01-23

Applicant: RAYTHEON COMPANY

Inventor： BUELL, David ,  VAMPOLA, John, L. ,  HARRIS, Micky, R. ,  BOTTS, Steven

IPC: H04N5/33 ,  H04N5/225

CPC classification number: H04N5/23245 ,  H04N5/2257 ,  H04N5/2259 ,  H04N5/257 ,  H04N5/33 ,  H04N5/378 ,  H04N9/09 ,  H04N9/10 ,  H04N2201/0452 ,  H04N2201/0458 ,  H04N2209/048

Abstract: A combined scanning and staring (SCARING) focal plane array (FPA) imaging system having a plurality of modes of operation is provided. In one example, the SCARING FPA system includes a photodetector array with a plurality of photodetectors arranged in a plurality of photodetector rows, a readout integrated circuit (ROIC) coupled to the photodetector array, and a processor coupled to the ROIC. The processor coupled to the ROIC is configured to dynamically configure the SCARING FPA between a scanning mode of operation and a staring mode of operation.

Abstract translation: 提供具有多种操作模式的组合扫描和盯着（SCARING）焦平面阵列（FPA）成像系统。 在一个示例中，SCARING FPA系统包括具有布置在多个光电检测器行中的多个光电检测器的光电检测器阵列，耦合到光电检测器阵列的读出集成电路（ROIC）和耦合到ROIC的处理器。 耦合到ROIC的处理器被配置为在扫描操作模式和盯着操作模式之间动态地配置SCARING FPA。

公开(公告)号：WO2015005992A1

公开(公告)日：2015-01-15

申请号：PCT/US2014/040675

申请日：2014-06-03

Applicant: RAYTHEON COMPANY

Inventor： HARRIS, Micky, R.

IPC: H03K3/012 ,  H03K3/037 ,  H03K3/356 ,  H03K3/3562

CPC classification number: H03K3/012 ,  H03K3/0372 ,  H03K3/356121 ,  H03K3/356156 ,  H03K3/35625

Abstract: A flip-flop having a first storage circuit having a first input fed by the true logic signal and a second input fed by the complement of the logic signal. A second storage circuit has a pair of inputs coupled to the first storage circuit. In response to one clock signal: the first storage circuit passes the true and complement logic signals for storage therein while the second storage circuit prevents the true and complement logic signals stored in the first storage circuit from passing to the second circuit. In response to a subsequent clock signal; the first storage circuit prevents the true and complement logic signals from passing for storage in the first storage circuit while the second storage circuit passes the true and complement logic signals stored in the first storage circuit at the outputs of the first storage circuit to the second storage circuit for storage therein.

Abstract translation: 一种具有第一存储电路的触发器，该第一存储电路具有由真实逻辑信号馈送的第一输入和由该逻辑信号的补码馈送的第二输入。 第二存储电路具有耦合到第一存储电路的一对输入。 响应于一个时钟信号：第一存储电路通过真实和补码逻辑信号以存储在其中，而第二存储电路防止存储在第一存储电路中的真实和补码逻辑信号传递到第二电路。 响应随后的时钟信号; 第一存储电路防止真实和补码逻辑信号通过以存储在第一存储电路中，而第二存储电路将存储在第一存储电路中的第一存储电路中的真和补逻辑信号在第一存储电路的输出端传递到第二存储器 电路用于存储。

公开(公告)号：EP2387799A1

公开(公告)日：2011-11-23

申请号：EP10700191.9

申请日：2010-01-07

Applicant: Raytheon Company

Inventor： VAMPOLA, John, L. ,  HARRIS, Micky, R.

IPC: H01L27/146

CPC classification number: H01L27/14643 ,  H01L27/14609

Abstract: A unit cell includes a MOSFET and an integration capacitor. The MOSFET includes a source, a drain, and a gate. The drain is coupled to the source, and the MOSFET is operable to store a first portion of an electric charge corresponding to a detected light intensity. The integration capacitor includes a first end and a second end. The first end is coupled to the drain of the MOSFET and the second end is coupled to a ground. The integration capacitor is operable to store a second portion of the electric charge corresponding to the detected light intensity.