中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

34 records (took 0.021 seconds)

    Switch circuits
    2.
    发明公开
    Switch circuits 失效
    Schaltkreise zum Schalten。

    公开(公告)号：EP0533335A1

    公开(公告)日：1993-03-24

    申请号：EP92307141.9

    申请日：1992-08-05

    Applicant: RAYTHEON COMPANY

    Inventor： Russell, Mark E. ,  Daly III, Edward G. ,  Mara Jr., John R.

    IPC: H03K17/56

    CPC classification number: H03K17/693 ,  H03K17/162

    Abstract: A radio frequency switch circuit (14) includes a first RF switch (18) having a first common port (18a) coupled to an input port (14a) of the circuit (14) and a first pair of branch ports (18b,18c) and a second RF switch (28) having a second common port (28a) coupled (30) to an output port (14b) of the circuit (14) and a second pair of branch ports (28b,28c). An Rf propagation network (26) has a first end coupled to a first one (18b) of said first pair of branch ports (18b,18c) of said first RF switch (18) and a second end coupled to a first one (28b) of said second pair of branch ports (28b,28c) of said second RF switch (28). An Rf termination (24) having an impedance characteristic corresponding to an impedance characteristic of said first common port (18a) has a first end coupled to a second one (18c) of said first pair of branch ports (18b,18c) of said first RF switch (18) and a second end coupled to a first reference potential.

    Abstract translation: 射频开关电路（14）包括具有耦合到电路（14）的输入端口（14a）的第一公共端口（18a）和第一对分支端口（18b，18c）的第一RF开关（18） 以及具有与电路（14）的输出端口（14b）耦合（30）的第二公共端口（28a）和第二对分支端口（28b，28c）的第二RF开关（28）。 Rf传播网络（26）具有耦合到所述第一RF开关（18）的所述第一对分支端口（18b，18c）中的第一端（18b）的第一端和耦合到第一RF开关（18b）的第二端 ）所述第二RF开关（28）的所述第二对分支端口（28b，28c）。 具有对应于所述第一公共端口（18a）的阻抗特性的阻抗特性的Rf终端（24）具有耦合到所述第一公共端口（18a）的所述第一对分支端口（18b，18c）中的第二端（18c）的第一端 RF开关（18）和耦合到第一参考电位的第二端。

    Frequency multiplier
    3.
    发明公开
    Frequency multiplier 失效
    Frequenzvervielfacher。

    公开(公告)号：EP0521652A2

    公开(公告)日：1993-01-07

    申请号：EP92305845.7

    申请日：1992-06-25

    Applicant: RAYTHEON COMPANY

    Inventor： Russell, Mark E. ,  Pietrangelo, Gregory J. ,  Mara, John F., Jr. ,  Tipton, Michael C

    IPC: H03B19/16

    CPC classification number: H03B19/18 ,  H03B19/00 ,  H03B19/16 ,  H03B2200/0028 ,  H03B2200/0088 ,  H03L5/00

    Abstract: A frequency doubler (Fig. 7) or a frequency tripler (Fig. 4) is coupled to an amplifier (110) with a temperature compensation circuit (126) and a feed forward gain control loop (114,120,122,124,116). With such an arrangement, a frequency multiplier is provided wherein variations of an output signal of the frequency multiplier due to changing characteristics of the frequency multiplier caused by ambient temperature variation or from a varying input signal level are minimized. An anti-parallel pair of diodes (136a,136b) provides odd harmonics from an amplified (132) input RF signal. A high pass filter (138) selects the third harmonic and supplies it through an amplifier (112) and a coupler (114) to a variable attenuator (116). The coupler (114) supplies a signal to a detector (120) that drives one input of a differential amplifier (124). The temperature compensation circuit (126) supplies a reference signal to the other input of the differential amplifier (124). The output from the differential amplifier (124) is a control signal that controls the attenuator (116) to compensate for variations in the amplitude of the output from the high pass filter (138) and variation in the characteristics of the amplifiers (112,118) due to temperature change.

    Abstract translation: 倍频器（图7）或频率三倍（图4）通过温度补偿电路（126）和前馈增益控制回路（114,120,122,124,116）耦合到放大器（110）。 通过这种布置，提供了一种倍频器，其中由于由环境温度变化或变化的输入信号电平引起的倍频器特性的变化导致的倍频器的输出信号的变化被最小化。 反并联的二极管（136a，136b）从放大的（132）输入RF信号提供奇次谐波。 高通滤波器（138）选择三次谐波，并通过放大器（112）和耦合器（114）将其提供给可变衰减器（116）。 耦合器（114）向驱动差分放大器（124）的一个输入端的检测器（120）提供信号。 温度补偿电路（126）将参考信号提供给差分放大器（124）的另一个输入端。 来自差分放大器（124）的输出是控制信号，其控制衰减器（116）以补偿来自高通滤波器（138）的输出的幅度的变化和放大器（112,118）的特性的变化 到温度变化。

    Pin diode driver circuit with DC bias terminal and timing delay circuit for high power HF input protection of radar low-noise amplifier
    8.
    发明公开
    Pin diode driver circuit with DC bias terminal and timing delay circuit for high power HF input protection of radar low-noise amplifier 失效
    与DC参考电压和延迟电路PIN二极管驱动器电路，以保护高功率RF（干扰）信号的雷达输入放大器。

    公开(公告)号：EP0534680A1

    公开(公告)日：1993-03-31

    申请号：EP92308477.6

    申请日：1992-09-17

    Applicant: RAYTHEON COMPANY

    Inventor： Russell, Mark E. ,  Miller, David C.

    IPC: G01S13/00 ,  H02H9/00

    CPC classification number: H03K17/74 ,  H03K17/667

    Abstract: A timing delay circuit (34) includes a first transistor (Q5) having a control electrode (Q5B) coupled to an input terminal (34a), a reference electrode (Q5C) coupled to a first DC bias terminal (28a) and an output electrode (Q5E) coupled to an output terminal (34b) of the timing delay circuit (34); a second transistor (Q6) having a control electrode (Q6B) coupled to the input terminal (34a), a reference electrode (Q6C) coupled to a second bias terminal (28b) and an output electrode (Q6E); and a third transistor (Q7) having a control electrode (Q7B) coupled to the output electrode (Q6E) of the second transistor (Q6), a reference electrode (Q7C) coupled to the second bias terminal (28b) and an output electrode (Q7E) coupled to the output terminal (34b) of the timing delay circuit (34). The timing delay circuit (34) is the output stage of a driver circuit (28) for a PIN diode (36) which acts as a limiter between a radar transmit/receive duplexor (14) and the radar receiver (20). Control logic signals are applied to a line circuit (24) and converted into signals of suitable voltage and current by a CCD device (26), a voltage translator circuit (30), and a current amplifier (32) before application to the input terminal (34a) of the timing delay circuit (34), which ensures rapid switching.

    Abstract translation: 定时延迟电路（34）包括第一晶体管（Q5），其具有耦合到第一DC偏置端子（28a）的输入端（34A），一个参比电极（Q5C）耦合到控制电极（Q5B）和输出电极 在输出端耦合到（Q5E）（34b）的定时延迟电路（34）; 耦合到第二偏压端子的第二晶体管（Q6），其具有耦合到所述输入端子（34A），一个参比电极（Q6C）的控制电极（Q6B）（28B）和输出电极（Q6E）; 和耦合到所述第二偏置端子的第三晶体管（Q7）具有耦合到所述第二晶体管（Q6），参比电极（Q7C）的输出电极（Q6E）的控制电极（Q7B）（28B）和输出电极（ Q7E）耦合到输出端子（34b）的定时延迟电路（34）。 定时延迟电路（34）为PIN二极管（36），其用作雷达发射之间的限幅器的驱动器电路（28）的输出级/接收双工器（14）和雷达接收机（20）。 控制逻辑信号被施加到一个用户线电路（24）和施加到输入端之前被转换成合适的电压和电流的信号由CCD设备（26），一个电压转换器电路（30），和一个电流放大器（32） 定时延迟电路（34），这确保了快速切换的（34A）。

Patent Agency Ranking