公开(公告)号：US20040213064A1

公开(公告)日：2004-10-28

申请号：US10671795

申请日：2003-09-29

Applicant: RENESAS TECHNOLOGY CORP.

Inventor： Takayuki Gyohten ,  Masaru Haraguchi ,  Fukashi Morishita

IPC: G11C007/00

CPC classification number: G11C11/4096 ,  G11C7/06 ,  G11C11/4091 ,  G11C2207/002 ,  G11C2207/065

Abstract: A connection gate circuit includes first and second N channel MOS transistors connected in series between a first bit line of a pair of bit lines and a first global IO line of a pair of IO lines, and third and fourth N channel MOS transistors connected in series between a second bit line of the pair of bit lines and a second global IO line of the pair of IO lines. The first and second N channel MOS transistors have their gates receiving a sense amplifier activation signal activating a sense amplifier. The third and fourth N channel MOS transistors have their gates receiving a column selection signal.

Abstract translation: 连接门电路包括串联连接在一对位线的第一位线和一对IO线的第一全局IO线之间的第一和第二N沟道MOS晶体管，以及串联连接的第三和第四N沟道MOS晶体管 在所述一对位线的第二位线与所述一对IO线的第二全局IO线之间。 第一和第二N沟道MOS晶体管的栅极接收激活读出放大器的读出放大器激活信号。 第三和第四N沟道MOS晶体管的栅极接收列选择信号。

公开(公告)号：US20040201062A1

公开(公告)日：2004-10-14

申请号：US10653198

申请日：2003-09-03

Applicant: RENESAS TECHNOLOGY CORP.

Inventor： Masakazu Hirose ,  Fukashi Morishita

IPC: H01L027/01

CPC classification number: H01L27/1203 ,  H01L21/84

Abstract: In a potential interconnection layer, when viewed from a plane, a plurality of power supply potential regions and ground potential regions are alternately provided, with an interlayer insulation layer lying therebetween. A contact plug penetrating a second insulation layer is provided to electrically connect a source/drain (S/D) region on one side of a selected field effect transistor with a selected power supply potential region. Similarly, a contact plug penetrating the second insulation layer is provided to electrically connect a source/drain (S/D) region on the other side of another selected field effect transistor with a selected ground potential region. By employing this structure, a semiconductor device having a plurality of semiconductor circuits in which a power supply potential and a ground potential can be stabilized regardless of the cross-sectional structure of the semiconductor device is provided.

Abstract translation: 在潜在的互连层中，当从平面观察时，交替地设置多个电源电位区域和接地电位区域，层间绝缘层位于其间。 提供穿透第二绝缘层的接触插塞以将选定的场效应晶体管的一侧上的源极/漏极（S / D）区域与选定的电源电位区域电连接。 类似地，穿过第二绝缘层的接触插塞被提供以将另一个选择的场效应晶体管的另一侧上的源极/漏极（S / D）区域与选择的接地电位区域电连接。 通过采用这种结构，提供了具有能够稳定电源电位和接地电位的多个半导体电路的半导体器件，而与半导体器件的横截面结构无关。