公开(公告)号：WO2014031813A4

公开(公告)日：2014-05-30

申请号：PCT/US2013056105

申请日：2013-08-22

Applicant: RF MICRO DEVICES INC

Inventor： RITENOUR ANDREW P

IPC: H01C7/12 ,  H01L27/02

CPC classification number: H01L27/0629 ,  H01L27/0248 ,  H01L29/2003 ,  H01L29/778

Abstract: A semiconductor device with electrical overstress (EOS) protection is disclosed. The semiconductor device includes a semi-insulating layer, a first contact disposed onto the semi-insulating layer, and a second contact disposed onto the semi-insulating layer. A passivation layer is disposed onto the semi-insulating layer. The passivation layer has a dielectric strength that is greater than that of the semi-insulating layer to ensure that a voltage breakdown occurs within the semi-insulating layer within a semi-insulating region between the first contact and the second contact before a voltage breakdown can occur in the passivation layer.

Abstract translation: 公开了具有电应力（EOS）保护的半导体器件。 半导体器件包括半绝缘层，设置在半绝缘层上的第一触点和设置在半绝缘层上的第二触点。 钝化层设置在半绝缘层上。 钝化层的绝缘强度大于半绝缘层的绝缘强度，以确保在电压击穿之前在第一接触件和第二接触件之间的半绝缘区域内的半绝缘层内发生电压击穿 发生在钝化层中。