公开(公告)号：US4805106A

公开(公告)日：1989-02-14

申请号：US73400

申请日：1987-07-09

Applicant: Randy D. Pfeifer

Inventor： Randy D. Pfeifer

IPC: G06F13/38 ,  G06F9/52 ,  G06F11/14 ,  G06F11/16 ,  G06F15/16 ,  G06F15/177 ,  G06F9/30 ,  G06F13/16

CPC classification number: G06F11/14 ,  G06F11/1666 ,  G06F11/2035 ,  G06F11/2043 ,  G06F9/52 ,  G06F2201/825

Abstract: To lock use of shared information to itself in a multiprocessor system (100) having two independently and asynchronously operating processors (101, 111) whose main store units (102, 112) duplicate each other's contents, a processor must cause an atomic read-modify-write (RMW) operation to be executed on a semaphore in the duplicated main store units of both processors. To properly order execution of multiple such RMW operations, arbiters (106, 116) of system buses (105, 115) of the two processors communicate over an interarbiter channel (121). The arbiter of a source processor that wishes to perform an RMW operation notifies the other processor's arbiter over the interarbiter channel. Simultaneous attempts at notification by both arbiters are resolved in favor of one of them that is designated the master. The notifying arbiter prevents its processor from performing another RMW operation until the one RMW operation has completed thereon, but permits other operations to proceed normally. The notified arbiter prevents its processor from performing another RMW operation until the one RMW operation has been transferred via interprocessor links (107, 117) and bus (120) from the source processor to the notified arbiter's processor and has been performed thereon, but permits other operations to proceed normally. Thus multiple RMW operations are performed on both processors in the same order asynchronously and without impacting performance of other operations.

Abstract translation: 为了在具有两个主存储单元（102,112）彼此重复的内容的两个独立和异步操作的处理器（101,111）的多处理器系统（100）中锁定对共享信息的使用，处理器必须引起原子读取修改 写入（RMW）操作将在两个处理器的重复主存储单元中的信号量上执行。 为了正确地订购多个这样的RMW操作的执行，两个处理器的系统总线（105,115）的仲裁器（106,116）通过间隔器通道（121）进行通信。 希望执行RMW操作的源处理器的仲裁器通过interarbiter通道通知其他处理器的仲裁器。 双方仲裁员通知的同时尝试均得到解决，主张被指定为主人的其中一人。 通知仲裁器防止其处理器执行另一个RMW操作，直到一个RMW操作在其上完成，但允许其他操作正常进行。 所通知的仲裁器防止其处理器执行另一个RMW操作，直到一个RMW操作已经通过处理器间链路（107,117）和总线（120）从源处理器传送到所通知的仲裁器的处理器并已在其上执行，但允许其他 操作正常进行。 因此，在两个处理器上以相同的顺序异步执行多个RMW操作，而不会影响其他操作的性能。

公开(公告)号：US5848136A

公开(公告)日：1998-12-08

申请号：US770283

申请日：1996-12-20

Applicant: Roger W. Ratz ,  Randy D. Pfeifer

Inventor： Roger W. Ratz ,  Randy D. Pfeifer

IPC: H04M1/60 ,  H04M11/00

CPC classification number: H04M1/6033

Abstract: There is disclosed a telephone instrument having controller and audio unit portions coupled together by a control bus and a user data bus having four audio states. The audio unit portion comprises a state machine that allows operating modes of the telephony instrument to be monitored and controlled. The state machine places the user data bus in a first predetermined state and the controller portion responds by placing the control bus in a selected state. The state machine detects the selected state and, in response thereto, places the user data bus in a second predetermined state. The second predetermined state indicates whether the first predetermined state was intended to be one of the four audio states or one of at least two mode control states. The user data bus and the control bus cooperate to provide a sequential output having at least six states, thereby allowing the operating modes to be monitored and controlled without modifying the bus drive circuitry.

Abstract translation: 公开了一种具有由控制总线和具有四个音频状态的用户数据总线耦合在一起的控制器和音频单元部分的电话设备。 音频单元部分包括状态机，其允许监视和控制电话乐器的操作模式。 状态机将用户数据总线置于第一预定状态，并且控制器部分通过将控制总线置于选择状态来进行响应。 状态机检测所选择的状态，并且响应于此，将用户数据总线置于第二预定状态。 第二预定状态指示第一预定状态是否意图是四个音频状态中的一个或至少两个模式控制状态中的一个。 用户数据总线和控制总线协同提供具有至少六个状态的顺序输出，从而允许在不修改总线驱动电路的情况下监视和控制操作模式。

公开(公告)号：US5666407A

公开(公告)日：1997-09-09

申请号：US567521

申请日：1995-12-05

Applicant: Randy D. Pfeifer

Inventor： Randy D. Pfeifer

IPC: H04M1/60 ,  H04M3/56 ,  H04M9/08

CPC classification number: H04M3/56 ,  H04M3/568

Abstract: A software-implemented bridging routine is provided for a full duplex audio telephone system comprising units A, B and C. of which only unit A need have at least two lines and be full duplex. Unit A receives and speaker-reproduces an audio signal B+C that echoes with a time delay dt.sub.1 and is detected by unit A's microphone as a signal k.sub.b Bdt.sub.1 +k.sub.c Cdt.sub.1, where k.sub.b and k.sub.c are co-efficients. Unit A's host software determines time dt.sub.1 and generates a delay dt.sub.2 .apprxeq.dt.sub.1. Unit A's host processor sums its own microphone output with a signal generated by a non-destination unit that is delayed by time dt.sub.2. Thus, when communicating with unit B, unit A's software generates a host processor output signal A+k.sub.b Bdt.sub.1 +k.sub.c Cdt.sub.1 +Cdt.sub.2. The k.sub.b Bdt.sub.1 echo component is removed by unit A's AEC, which is coupled between units A and B. This causes unit B to receive the signal A+Cdt.sub.2 +k.sub.c Cdt.sub.1 from unit A. Since dt.sub.2 .apprxeq.dt.sub.1, user B hears voice A summed with a slightly delayed voice C (e.g., Cdt.sub.2) superimposed with an attenuated in-phase version of voice C (e.g., k.sub.c Cdt.sub.1). User B thus hears user A's voice and user C's voice conversing naturally in a full duplex manner. Similarly, B hears user A and user C conversing, and user C hears user A and user B conversing. In this fashion, full-duplex operation is achieved without using hardware bridge circuitry.

Abstract translation: 为包括单元A，B和C的全双工音频电话系统提供软件实现的桥接例程，其中仅单元A需要具有至少两行并且是全双工。 单元A接收和扬声器再现以时间延迟dt1回波的音频信号B + C，并且由单元A的麦克风检测为信号kbBdt1 + kcCdt1，其中kb和kc是系数。 单元A的主机软件确定时间dt1并产生延迟dt2 APPROX dt1。 单元A的主机处理器将自己的麦克风输出与由目的地单元生成的信号相加，延迟时间dt2。 因此，当与单元B通信时，单元A的软件产生主机处理器输出信号A + kbBdt1 + kcCdt1 + Cdt2。 单元A的AEC除以单元A和A之间的kbBdt1回波分量，使单元B从单元A接收信号A + Cdt2 + kcCdt1。由于dt2 APPROX dt1，用户B听到A 与语音C的衰减同相版本（例如，kcCdt1）叠加的稍微延迟的语音C（例如，Cdt2）。 用户B因此听到用户A的语音和用户C的语音自然地以全双工方式进行通话。 类似地，B听到用户A和用户C的交谈，用户C听到用户A和用户B的对话。 以这种方式，在不使用硬件桥接电路的情况下实现全双工操作。

公开(公告)号：US4835737A

公开(公告)日：1989-05-30

申请号：US888498

申请日：1986-07-21

Applicant: Hanz W. Herrig ,  David N. Horn ,  Daniel V. Peters ,  Randy D. Pfeifer ,  Wayne R. Wilcox

Inventor： Hanz W. Herrig ,  David N. Horn ,  Daniel V. Peters ,  Randy D. Pfeifer ,  Wayne R. Wilcox

IPC: G06F1/18 ,  G06F3/00 ,  G06F13/40 ,  H05K7/14

CPC classification number: H05K7/1414 ,  G06F13/4081

Abstract: An electronic circuit board electrically connected to other circuits of a data processing system by means of a bus, may be removed and re-inserted in the system without the necessity of disabling other circuits connected to the bus. A latch actuated switch provides a control signal in anticipation of circuit board removal. The control signal activates a finite state machine which seizes control of the bus after completion of any current bus communications and stops the generation of clock pulses normally required in bus communications. When contact is physically broken between the board and its corresponding connector, the finite state machine restores the bus clock pulses and relinquishes control of the bus. When a board is to be inserted in an open connector, contact between the board and the connector is sensed by the finite state machine which causes the bus to be seized and the bus clock pulses to be temporarily inhibited. When the board is fully inserted, the finite state machine restores the bus clock pulses and relinquishes control of the bus.

Abstract translation: 通过总线电连接到数据处理系统的其他电路的电子电路板可以被去除并重新插入系统中，而不需要禁用连接到总线的其他电路。 闩锁致动开关提供控制信号，预期电路板移除。 控制信号激活一个有限状态机，在完成任何当前的总线通信之后占用总线的控制，并停止在总线通信中通常需要的时钟脉冲的产生。 当板与其相应的连接器之间的接触物理断开时，有限状态机恢复总线时钟脉冲并放弃总线的控制。 当一个电路板插入一个开放的连接器时，板和连接器之间的接触由有限状态机检测到，这导致总线被占用，并且总线时钟脉冲被暂时禁止。 当板完全插入时，有限状态机恢复总线时钟脉冲并放弃总线的控制。