公开(公告)号：SG10201911466SA

公开(公告)日：2020-01-30

申请号：SG10201911466S

申请日：2018-07-17

Applicant: SAMSUNG ELECTRONICS CO LTD

Inventor： JIYOUNG KIM ,  KISEOK LEE ,  BONG-SOO KIM ,  JUNSOO KIM ,  DONGSOO WOO ,  KYUPIL LEE ,  HYEONGSUN HONG ,  YOOSANG HWANG

Abstract: The present invention relates to a semiconductor memory device. More specifically, the semiconductor memory device comprises: a plurality of memory cell transistors vertically stacked on a substrate; a first conductive line connected to a source of at least one of the memory cell transistors; a second conductive line connected to gates of the memory cell transistors; and a capacitor connected to a drain of at least one of the memory cell transistors. The capacitor includes a first electrode horizontally extended in a first direction parallel to the upper surface of the substrate from the drain. One of the first and second conductive lines horizontally extends in a second direction intersecting the first direction, and the other one of the first and second conductive lines vertically extends in a third direction perpendicular to the upper surface of the substrate.

公开(公告)号：SG10201806114YA

公开(公告)日：2019-04-29

申请号：SG10201806114Y

申请日：2018-07-17

Applicant: SAMSUNG ELECTRONICS CO LTD

Inventor： JIYOUNG KIM ,  KISEOK LEE ,  BONG-SOO KIM ,  JUNSOO KIM ,  DONGSOO WOO ,  KYUPIL LEE ,  HYEONGSUN HONG ,  YOOSANG HWANG

Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes a substrate. The semiconductor memory device includes a plurality of memory cell transistors vertically stacked on the substrate. The semiconductor memory device includes a first conductive line connected to a source region of at least one of the plurality of memory cell transistors. The semiconductor memory device includes a second conductive line connected to a plurality of gate electrodes of the plurality of memory cell transistors. Moreover, the semiconductor memory device includes a data storage element connected to a drain region of the at least one of the plurality of memory cell transistors. FIG. 26