公开(公告)号：US20240324246A1

公开(公告)日：2024-09-26

申请号：US18594355

申请日：2024-03-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiyeon YANG ,  Donggeon GU ,  Bonwon KOO ,  Jeonghee PARK ,  Hajun SUNG ,  Dongho AHN ,  Zhe WU ,  Changseung LEE ,  Minwoo CHOI

IPC: H10B63/00 ,  H10N70/00

CPC classification number: H10B63/24 ,  H10B63/84 ,  H10N70/841 ,  H10N70/8825 ,  H10N70/8828

Abstract: Provided are a self-selecting memory device having polarity dependent threshold voltage shift characteristics and/or a memory apparatus including the self-selecting memory device. The memory device includes a first electrode, a second electrode apart from and facing the first electrode, and a memory layer between the first electrode and the second electrode. The memory layer has Ovonic threshold switching characteristics and is configured to have a threshold voltage of the memory layer be changed as a density of active traps in the memory layer is changed, the threshold voltage changing according to the polarity and the intensity of a bias voltage applied to the memory layer. Furthermore, an element composition distribution is configured to be maintained constant in the memory layer in response to the threshold voltage of the memory layer changing.

公开(公告)号：US20240032308A1

公开(公告)日：2024-01-25

申请号：US18478776

申请日：2023-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wooyoung YANG ,  Bonwon KOO ,  Chungman KIM ,  Kwangmin PARK ,  Hajun SUNG ,  Dongho AHN ,  Changseung LEE ,  Minwoo CHOI

IPC: H10B63/00 ,  G11C13/00 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H10N70/20 ,  H10N70/00

CPC classification number: H10B63/24 ,  G11C13/0004 ,  H10B61/10 ,  H10B63/84 ,  H10N50/01 ,  H10N50/80 ,  H10N70/24 ,  H10N70/25 ,  H10N70/063 ,  H10N70/231 ,  H10N70/8413 ,  H10N70/8825 ,  H10N70/8828 ,  H10N70/8833 ,  H10N70/8836

Abstract: A chalcogen compound layer exhibiting ovonic threshold switching characteristics, a switching device, a semiconductor device, and/or a semiconductor apparatus including the same are provided. The switching device and/or the semiconductor device may include two or more chalcogen compound layers having different energy band gaps. Alternatively, the switching device and/or semiconductor device may include a chalcogen compound layer having a concentration gradient of an element of boron (B), aluminum (Al), scandium (Sc), manganese (Mn), strontium (Sr), and/or indium (In) in a thickness direction thereof. The switching device and/or a semiconductor device may exhibit stable switching characteristics while having a low off-current value (leakage current value).

公开(公告)号：US20250133970A1

公开(公告)日：2025-04-24

申请号：US18444206

申请日：2024-02-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minwoo CHOI ,  Hajun SUNG ,  Bonwon KOO ,  Kiyeon YANG ,  Changseung LEE

IPC: H10N70/00 ,  G11C13/00 ,  H10B63/00

Abstract: Provided are a chalcogenide-based memory device capable of implementing multi-level memory and an electronic apparatus including the chalcogenide-based memory device. The memory device includes a first electrode and a second electrode arranged to be spaced apart from each other, and a memory layer provided between the first electrode and the second electrode and including a plurality of memory material layers having different threshold voltages from each other. Each of the plurality of memory material layers includes a chalcogenide-based material, has an ovonic threshold switching (OTS) characteristic, and is configured to have a threshold voltage varying depending on a polarity and intensity of an applied voltage.

公开(公告)号：US20220406844A1

公开(公告)日：2022-12-22

申请号：US17568866

申请日：2022-01-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chungman KIM ,  Bonwon KOO ,  Dongho AHN ,  Kiyeon YANG ,  Zhe WU ,  Chang Seung LEE

IPC: H01L27/24 ,  H01L45/00

Abstract: A resistive memory device including a resistive memory pattern; and a selection element pattern electrically connected to the resistive memory pattern, the selection element pattern including a chalcogenide switching material and at least one metallic material, the chalcogenide switching material including germanium, arsenic, and selenium, and the at least one metallic material including aluminum, strontium, or indium, wherein the selection element pattern includes an inhomogeneous material layer in which content of the at least one metallic material in the selection element pattern is variable according to a position within the selection element pattern.

公开(公告)号：US20220149114A1

公开(公告)日：2022-05-12

申请号：US17362075

申请日：2021-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiyeon YANG ,  Bonwon KOO ,  Segab KWON ,  Chungman KIM ,  Yongyoung PARK ,  Dongho AHN ,  Seunggeun YU ,  Changseung LEE

IPC: H01L27/24 ,  H01L45/00 ,  H01L29/24

Abstract: Provided are a chalcogen compound having ovonic threshold switching characteristics, and a switching device, a semiconductor device, and/or a semiconductor apparatus which include the chalcogen compound. The chalcogen compound includes five or more elements and may have stable switching characteristics with a low off-current value (leakage current value). The chalcogen compound includes: selenium (Se) and tellurium (Te); a first element comprising at least one of indium (In), aluminum (Al), strontium (Sr), and calcium (Ca); and a second element including germanium (Ge) and/or tin (Sn), and may further include at least one of arsenic (As), antimony (Sb), and bismuth (Bi).

公开(公告)号：US20190087044A1

公开(公告)日：2019-03-21

申请号：US16134471

申请日：2018-09-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunhyoung CHO ,  Bonwon KOO ,  Hyunjoon KIM ,  Haesung KIM ,  Jungyun WON

IPC: G06F3/041 ,  H01L27/32 ,  G06F3/044 ,  G06K9/00

CPC classification number: G06F3/0412 ,  G06F3/044 ,  G06K9/0002 ,  H01L27/323 ,  H01L27/3234 ,  H01L27/3244

Abstract: Provided are a pattern structure for preventing a moiré pattern from becoming visible, and a display apparatus using the same. The pattern structure includes a first element pattern including a plurality of first elements arranged regularly at a first pitch; a second element pattern including a plurality of second elements arranged regularly at a second pitch, the second element pattern being provided on the first element pattern; and a filling layer configured to fill gaps among the plurality of second elements, between adjacent ones thereof. A difference between transmittances of the second element and the filling layer is about 5% or less and thus, a moiré pattern occurring due to the overlapping of the first element pattern and the second element pattern may be prevented from becoming visible.

公开(公告)号：US20250149084A1

公开(公告)日：2025-05-08

申请号：US18785752

申请日：2024-07-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changseung LEE ,  Minwoo CHOI ,  Bonwon KOO ,  Hajun SUNG ,  Kiyeon YANG

IPC: G11C11/56 ,  H10B63/00 ,  H10B99/00

Abstract: Provided are a memory device for implementing a multi-level memory and a method of implementing a multi-level memory by using the memory device. The memory device includes first and second electrodes apart from each other, a self-selecting memory layer between the first and second electrodes having an ovonic threshold switching characteristic, including a chalcogenide-based material, and configured to have a threshold voltage varying depending on a polarity of and strength of a voltage applied thereto, and a resistive memory layer between the second electrode and the self-selecting memory layer and having a resistance characteristic varying depending on a voltage applied thereto. The memory device is configured to implement multi-level resistance states by changing at least one of a pulse polarity, a number of pulses, pulse height, and a pulse width of a voltage applied between the first and second electrodes.

公开(公告)号：US20240414926A1

公开(公告)日：2024-12-12

申请号：US18813539

申请日：2024-08-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wooyoung YANG ,  Bonwon KOO ,  Chungman KIM ,  Kwangmin PARK ,  Hajun SUNG ,  Dongho AHN ,  Changseung LEE ,  Minwoo CHOI

IPC: H10B63/00 ,  G11C13/00 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H10N70/00 ,  H10N70/20

Abstract: A chalcogen compound layer exhibiting ovonic threshold switching characteristics, a switching device, a semiconductor device, and/or a semiconductor apparatus including the same are provided. The switching device and/or the semiconductor device may include two or more chalcogen compound layers having different energy band gaps. Alternatively, the switching device and/or semiconductor device may include a chalcogen compound layer having a concentration gradient of an element of boron (B), aluminum (Al), scandium (Sc), manganese (Mn), strontium (Sr), and/or indium (In) in a thickness direction thereof. The switching device and/or a semiconductor device may exhibit stable switching characteristics while having a low off-current value (leakage current value).

公开(公告)号：US20190305049A1

公开(公告)日：2019-10-03

申请号：US16105259

申请日：2018-08-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungbae PARK ,  Wenxu XIANYU ,  Bonwon KOO ,  Takkyun RO ,  Changseung LEE

IPC: H01L27/30 ,  H01L51/44 ,  H01L27/146

Abstract: Provided are an image sensor and a method of manufacturing the same. The image sensor may include a plurality of light detection elements arranged to correspond to a plurality of pixel regions, a color filter layer on the plurality of light detection elements and including a plurality of color filters arranged to correspond to the plurality of light detection elements, and a photodiode device portion on the color filter layer. The photodiode device portion may have curved structures. The photodiode device portion may include an organic material-based photodiode layer, a first electrode between the photodiode layer and the color filter layer, and a second electrode on the photodiode layer. The photodiode device portion may have curved convex structures respectively corresponding to the plurality of color filters.

公开(公告)号：US20160026060A1

公开(公告)日：2016-01-28

申请号：US14633781

申请日：2015-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bonwon KOO ,  Deukseok CHUNG ,  Hyunjoon KIM ,  Shanghyeun PARK ,  Changsoo LEE ,  Taewon JEONG

IPC: G02F1/163 ,  G09G3/38 ,  G06F3/041 ,  G02F1/1333

CPC classification number: G02F1/163 ,  G02F1/13318 ,  G02F1/13338 ,  G02F2001/1635 ,  G06F3/0412 ,  G09G3/38 ,  G09G2310/08 ,  G09G2354/00

Abstract: An electro-chromic panel includes a detection layer, and an electro-chromic layer configured to switch an operational mode of a selected area according to a signal provided from the detection layer. A method of operating an electro-chromic panel includes detecting a first signal provided to a detection layer, and switching an operational mode of a first area of an electro-chromic layer according to the first signal provided from the detection layer.

Abstract translation: 电铬面板包括检测层和电色层，其被配置为根据从检测层提供的信号切换所选区域的操作模式。 操作电铬面板的方法包括检测提供给检测层的第一信号，以及根据从检测层提供的第一信号切换电致密层的第一区域的操作模式。