公开(公告)号：SG10201803335UA

公开(公告)日：2019-02-27

申请号：SG10201803335U

申请日：2018-04-20

Applicant: SAMSUNG ELECTRONICS CO LTD

Inventor： PHIL OUK NAM ,  JAEYOUNG AHN ,  SANGSOO LEE

IPC: H01L27/115

Abstract: Provided is a semiconductor device including a lower layer structure on a substrate, the lower layer structure having different thicknesses on first and second regions of the substrate, the lower layer structure including an electrode layer at a top and an insulating layer thereunder, an etch stop layer on the lower layer structure, an upper layer structure on the etch stop layer, the etch stop layer having an etch selectivity to the upper and lower layer structures, first and second contact plugs filling first and second openings defined in the upper layer structure and the etch stop layer on the first and second regions, respectively, and contacting corresponding electrode layers of the lower layer structure, respectively, such that one of the first and second contact plugs downwardly extends further with respect to a bottom of the etch stop layer than the other one of the first and second contact plugs. FIG. 5

公开(公告)号：US20210320123A1

公开(公告)日：2021-10-14

申请号：US17036594

申请日：2020-09-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SANGSOO LEE ,  CHAEHO KIM ,  WOOSUNG LEE ,  PHIL OUK NAM ,  JUNGGEUN JEE

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/11573 ,  H01L23/535

Abstract: Disclosed is a three-dimensional semiconductor memory device including a carbon-containing layer on a substrate, a plurality of electrode interlayer dielectric layers and a plurality of electrode layers that are alternately stacked on the carbon-containing layer, a cell vertical pattern that penetrates at least some of the electrode interlayer dielectric layers and the electrode layers, and a semiconductor pattern between the cell vertical pattern and the carbon-containing layer. The substrate includes a plurality of first grains. The semiconductor pattern includes a plurality of second grains. An average size of the second grains is less than an average size of the first grains.

公开(公告)号：US20190081054A1

公开(公告)日：2019-03-14

申请号：US15981928

申请日：2018-05-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNGGIL KIM ,  SANGSOO LEE ,  SEULYE KIM ,  HONGSUK KIM ,  JINTAE NOH ,  JI-HOON CHOI ,  JAEYOUNG AHN ,  SANGHOON LEE

IPC: H01L27/11556 ,  H01L27/11582 ,  G11C16/04 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor memory device has a plurality of gates vertically stacked on a top surface of a substrate, a vertical channel filling a vertical hole that extends vertically through the plurality of gates, and a memory layer in the vertical hole and surrounding the vertical channel. The vertical channel includes a bracket-shaped lower portion filling part of a recess in the top of the substrate and an upper portion extending vertically along the vertical hole and connected to the lower channel. At least one end of an interface between the lower and upper portions of the vertical channel is disposed at a level not than that of the top surface of the substrate.