公开(公告)号：US20240357803A1

公开(公告)日：2024-10-24

申请号：US18541559

申请日：2023-12-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongmin CHOI ,  Hyo-sub KIM ,  Sangkyu SUN ,  Junhyeok AHN ,  Jay-bok CHOI

IPC: H10B12/00

CPC classification number: H10B12/50 ,  H10B12/0335 ,  H10B12/482

Abstract: A semiconductor device may include a substrate including a cell block region and a peripheral region, which are adjacent to each other in a first direction, an active pattern on the cell block region, a bit line provided on the active pattern and extended in the first direction, a first insulating structure in contact with the bit line, and a contact plug electrically connected to the bit line. The bit line may include a first curved portion, a first linear portion connected to the first curved portion, and a first intervening portion connected to the first curved portion. The contact plug may be overlapped with the first curved portion.

公开(公告)号：US20220122986A1

公开(公告)日：2022-04-21

申请号：US17398136

申请日：2021-08-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sukhwa JANG ,  Kanguk KIM ,  Hyunsuk NOH ,  Yeongshin PARK ,  Sangkyu SUN ,  Sunyoung LEE ,  Sohyang LEE ,  Hongjun LEE ,  Hosun JUNG ,  Jeongmin JIN ,  Jeonghee CHOI ,  Jinseo CHOI ,  Cera HONG

IPC: H01L27/108

Abstract: A method of manufacturing a semiconductor device includes forming a lower structure including a plurality of transistors, forming a conductive layer on the lower structure, forming first preliminary pad mask patterns and wiring mask patterns on the conductive layer, forming pad mask patterns by patterning the first preliminary pad mask patterns while protecting the wiring mask patterns, and etching the conductive layer using the pad mask patterns and the wiring mask patterns as an etching mask to form pad patterns and wiring patterns.

公开(公告)号：US20240397707A1

公开(公告)日：2024-11-28

申请号：US18381785

申请日：2023-10-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangkyu SUN ,  Goro CHOI ,  Hyo-Sub KIM ,  Junhyeok AHN ,  Eunkyung CHA ,  Dongmin CHOI ,  Sanghyun CHOI

IPC: H10B12/00 ,  H01L29/423

Abstract: A semiconductor memory device includes a substrate having a cell array area and a core area near the cell array area, the cell array area including a direct contact hole exposing an active region, a buried contact in the cell array area, the buried contact being connected to a storage element, a direct contact in the cell array area, the direct contact including an upper layer and a lower layer, the upper layer including a metal, and the lower layer being in the direct contact hole in direct contact with the active region and including a silicide of the metal, bit lines in contact with the upper layer of the direct contact, and word lines crossing the bit lines.

公开(公告)号：US20240179893A1

公开(公告)日：2024-05-30

申请号：US18216745

申请日：2023-06-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangkyu SUN ,  Hyunyong KIM ,  Hyun-Jung KIM ,  Junhee PARK ,  Kyuwon WOO ,  Jiwon OH ,  Yoonyoung CHOI

IPC: H10B12/00

CPC classification number: H10B12/485 ,  H10B12/053 ,  H10B12/315 ,  H10B12/34 ,  H10B12/482

Abstract: A semiconductor device includes a substrate that includes an element separation film, an active region defined by the element separation film and arranged in a first direction, and a trench positioned across the active region and the element separation film, a bit line contact that is positioned within the trench and is connected to the active region, a bit line structure that is connected to the substrate through the bit line contact and that extends in a second direction different from the first direction across the active region, and a first contact spacer, a second contact spacer, and a third contact spacer within the trench and around the bit line contact, the first contact spacer being continuous within the trench, and each of the second contact spacer and the third contact spacer being separated into at least two discrete parts within the trench.