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    INSPECTION APPARATUS FOR SEMICONDUCTOR INTEGRATED CIRCUIT BY PULSE-SHAPED LASER BEAM
    1.
    发明专利
    INSPECTION APPARATUS FOR SEMICONDUCTOR INTEGRATED CIRCUIT BY PULSE-SHAPED LASER BEAM 失效

    公开(公告)号：JP2001255354A

    公开(公告)日：2001-09-21

    申请号：JP2001000668

    申请日：2001-01-05

    Applicant: SCHLUMBERGER TECHNOLOGIES INC

    Inventor： KASAPI STEVEN A ,  TSAO CHUN-CHENG ,  SOMANI SEEMA

    IPC: G01R31/26 ,  G01N21/00 ,  G01N21/01 ,  G01R1/06 ,  G01R15/24 ,  G01R31/302 ,  G01R31/308 ,  H01L21/66

    Abstract: PROBLEM TO BE SOLVED: To provide an inspection apparatus, for a semiconductor integrated- circuit device, which reduces the influence of a noise and which uses laser optical pulses. SOLUTION: A laser is used to inspect a specimen semiconductor integrated- circuit device. A single laser optical pulse from one laser light source is split into two optical pulses, and both of the two optical pulses are made incident on the device to be inspected. The two optical pulses are separated after their interaction with the device to be inspected, and the optical pulses are detected by two photodetectors. Two outputs from the photodetectors are subtracted mutually. By their subtraction, a common-mode which is induced by the two pulses such as a noise caused by the mechanical vibration of the device to be inspected, various noises from the laser light source or the like is erased. Their difference signal is used to extract a time change signal in the device to be inspected.

    4.
    发明专利
    未知

    公开(公告)号：DE10100816A1

    公开(公告)日：2001-07-19

    申请号：DE10100816

    申请日：2001-01-10

    Applicant: SCHLUMBERGER TECHNOLOGIES INC

    Inventor： KASAPI STEVEN A ,  TSAO CHUN-CHENG ,  SOMANI SEEMA

    IPC: G01R31/26 ,  G01N21/00 ,  G01N21/01 ,  G01R1/06 ,  G01R15/24 ,  G01R31/302 ,  G01R31/308 ,  H01L21/66 ,  G01R31/311 ,  H01S3/098

    Abstract: A laser beam is used to probe an integrated circuit device under test. A single laser provides a single laser pulse which is divided into two pulses, both of which are incident upon the device under test. After the two pulses interact with the device under test, the two pulses are separated and detected by two photo detectors. The electrical signals output by the photo detectors are then subtracted, which cancels out any common mode noise induced on both pulses including noise due to mechanical vibration of the device under test and also any noise from the laser. The difference signal can be used to reproduce a time varying signal in the device under test.

    METHOD FOR THINNING AND POLISHING THE DIE OF INTEGRATED CIRCUITS
    5.
    发明申请
    METHOD FOR THINNING AND POLISHING THE DIE OF INTEGRATED CIRCUITS 审中-公开
    一体化电路的整理和抛光方法

    公开(公告)号：WO02072311A3

    公开(公告)日：2002-11-07

    申请号：PCT/US0207305

    申请日：2002-03-11

    Applicant: SCHLUMBERGER TECHNOLOGIES INC

    Inventor： TSAO CHUN-CHENG ,  VALLIANT JOHN

    IPC: B24B1/00 ,  B24B7/22 ,  B24B37/04 ,  B24B49/12

    CPC classification number: B24B49/12 ,  B24B7/228 ,  B24B37/042

    Abstract: A reliable, inexpensive "back side" thinning process, capable of globally thinning an integrated circuit die (4) to a target thickness of 10 microns, and maintaining a yield of at least 80%, for chip repair and/or failure analysis of the packaged die. The flip-chip packaged die is exposed at its backside (10) and mounted on a lapping machine (14) with the backside exposed. The thickness of the die is measured at at least five locations on the die. The lapping machine grinds the exposed surface of the die to a thickness somewhat greater than the target thickness. The exposed surface of the die is polished. The thickness of the die is again measured optically with high accuracy. Based on the thickness data collected, appropriate machine operating parameters for further grinding and polishing of the exposed surface are determined. Further grinding and polishing are performed. These steps are repeated until the target thickness is reached.

    Abstract translation: 一种可靠，廉价的“背面”稀释过程，能够将集成电路管芯（4）全局变薄至目标厚度为10微米，并保持至少80％的产量，用于芯片修复和/或故障分析 包装模具 倒装芯片封装的裸片在其背面（10）处露出，并安装在背面暴露的研磨机（14）上。 在模具上的至少五个位置处测量模具的厚度。 研磨机将模具的暴露表面研磨到稍大于目标厚度的厚度。 模具的暴露表面被抛光。 再次以高精度光学测量模具的厚度。 基于收集的厚度数据，确定用于进一步研磨和抛光暴露表面的合适的机器操作参数。 进行进一步研磨和抛光。 重复这些步骤，直到达到目标厚度。

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