公开(公告)号：EP0768758A1

公开(公告)日：1997-04-16

申请号：EP95830430.5

申请日：1995-10-12

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Gaibotti, Maurizio ,  Adduci, Francesco

IPC: H03K3/3562

CPC classification number: H03K3/35625

Abstract: A low-consumption and high-density D flip-flop circuit implementation, particularly for standard cell libraries, which comprises a master section (100) and a slave section (200); the master section comprises a master latch structure (5) and the slave section comprises a slave latch structure (6); the master structure (100) and the slave structure (100) are interposed between a power supply line (V DD ) and a ground line (7), and each structure is constituted by a first pair of transistors (8, 9; 12, 13) and by a second pair of transistors (10, 11; 14, 15). The particularity of the invention is that in the master latch structure (5) the transistors (8, 9) the source terminals whereof are connected to the power supply line (V DD ) and constitute a first one of the two pairs of transistors (8, 9; 10, 11) are P-channel MOS transistors, the source terminals of the second pair of transistors (10, 11) of the master latch structure (5) are connected to the respective drain terminals of an additional pair of transistors (24, 25), the source terminals whereof are connected to the ground line (7); same-phase clock signals (CK) are fed both to the master section (100) and to the slave section (200).

Abstract translation: 低消耗和高密度D触发器电路实现，特别是用于标准单元库，它包括一个主部分（100）和从段（200）; 主部分包括主锁存器结构（5）和从动部分包括从锁存器结构（6）; 主结构（100）和从结构（100）被一个电源线（VDD）和接地线（7）之间，并且每个结构是由第一对晶体管（8,9构成; 12,13 ），并用第二对晶体管（10，11的14，15）。 本发明的特殊性是在主锁存器结构（5）的晶体管那样（8,9）的源极端WHEREOF被连接到电源线（VDD），并构成两对晶体管中的第一个（8， 9; 10，11）是主锁存器结构（5）被连接到另外的一对晶体管的所述respectivement漏极端子的P沟道MOS晶体管，所述第二对晶体管（10的源极端子，11）（24 ，25），则源终端WHEREOF被连接到接地线（7）; 同相时钟信号（CK）被馈送到两个主部（100）和向从属部（200）。

公开(公告)号：EP0690558A1

公开(公告)日：1996-01-03

申请号：EP94830329.2

申请日：1994-07-01

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Adduci, Francesco

IPC: H03B1/00 ,  H03B5/36

CPC classification number: H03B5/364

Abstract: A one-pin integrateable crystal oscillator in a Colpitts configuration employs a differential amplifier as an input gain stage provided with a capacitive-transformer feedback network. An enhanced stability and independence from temperature variation, a high Q figure and a short start-up are achieved without requiring a relatively large area of integration.

Abstract translation: Colpitts配置中的单引脚可并行晶体振荡器采用差分放大器作为具有电容 - 变压器反馈网络的输入增益级。 在不需要相对较大的积分面积的情况下，实现了与温度变化的稳定性和独立性的高Q值和短的启动。 $$