公开(公告)号：EP0825589A1

公开(公告)日：1998-02-25

申请号：EP96830448.5

申请日：1996-08-07

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Bruccoleri, Melchiorre ,  Demicheli, Marco ,  Demicheli, Davide ,  Patti, Giuseppe

IPC: G11B5/00 ,  G11B5/596

CPC classification number: G11B5/59688 ,  G11B5/5534 ,  G11B5/59605

Abstract: A servo-demodulator for a pair of alternating signals generated by a magnetic disc read head and indicative of the position of the read head in relation to the centre of a recorded track, comprising a peak detector (5) for successively and individually sampling the amplitude of each of a plurality of peaks of the said pair of alternating signals, and a capacitor (9) periodically connected to the output of the peak detector (5) by a control logic (7) for deriving a weighted average of the various successively sampled amplitudes, obtaining an averaged measure of amplitude with high immunity to noise.

Abstract translation: 一种用于由磁盘读出头产生并指示读出头相对于记录磁道中心的位置的一对交变信号的伺服解调器，包括一个峰值检测器（5），用于连续地和单独地对振幅 以及一个由控制逻辑（7）周期性地连接到峰值检测器（5）的输出端的电容器（9），用于导出各种连续采样的加权平均值 振幅，获得对噪声具有高度免疫力的幅度的平均测量值。

公开(公告)号：EP0745921A1

公开(公告)日：1996-12-04

申请号：EP95830226.7

申请日：1995-05-31

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l. ,  CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Bruccoltri, Melchiorre ,  Cosentino, Gaetano ,  Demicheli, Marco ,  Patti, Giuseppe

IPC: G05F1/00 ,  G05F3/26 ,  G05F3/22

CPC classification number: G05F3/265 ,  G05F3/222

Abstract: The present invention relates to a current generator stage for integrated analog circuits of the type comprising a current source (2) inserted between a first reference supply voltage (Vdd) and a second fixed reference voltage (GND).
The stage 1 comprises also at least one current mirror circuit (5) operationally connected to the current source (2) to generate at least one output current and a bias circuit (10) operationally connected to the current source (2) to supply to this source a bias voltage.
The stage 1 is also characterized in that the bias circuit (10) comprises an energy storage circuit (11) which in a first circuit configuration is a combination of a first reactance (X1) and a second reactance (X2) when the current source (2) is in a first operational mode.
The energy storage circuit (11) is in a second circuit configuration to supply to the current source (2) a predetermined bias voltage when said current source (2) is in a second operating mode.

Abstract translation: 本发明涉及一种用于集成模拟电路的电流发生器级，其包括插入在第一参考电源电压（Vdd）和第二固定参考电压（GND）之间的电流源（2）。 级1还包括至少一个电流镜电路（5），其可操作地连接到电流源（2）以产生至少一个输出电流，以及可操作地连接到电流源（2）的偏置电路（10） 源偏置电压。 阶段1的特征还在于，偏置电路（10）包括能量存储电路（11），当电流源（11）在第一电路配置中是第一电抗（X1）和第二电抗（X2）的组合， 2）处于第一操作模式。 能量存储电路（11）处于第二电路结构，以在所述电流源（2）处于第二操作模式时向电流源（2）提供预定的偏置电压。

公开(公告)号：EP0718978A1

公开(公告)日：1996-06-26

申请号：EP94830586.7

申请日：1994-12-23

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l. ,  CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Bruccoleri, Melchiorre ,  Cosentino, Gaetano ,  Demicheli, Marco ,  Patti, Giuseppe

IPC: H03L7/089

CPC classification number: H03L7/0896

Abstract: A differential charge pump circuit employing a lowpass filter network which is chargeable and dischargeable by means of switchingly controlled current generators employs two identical current generators (Gb1, Gb2) for injecting the same current I in a substantially continuous manner, on the two significant nodes (A, B) of the lowpass filter and two pairs of identical, switchingly controlled current generators (Gc1, Gc2, Gc3, Gc4) connected to said nodes (A, B), respectively, each capable of pulling a current I. The two generators forming each of said two pairs are controlled by one of a pair of control signals (UP, DOWN) and by the inverted signal of the other of said pair of control signals, respectively. All four, switchingly controlled generators may be of the same type (N-type), thus ensuring high speed and precision. The two (P-type) current generators (Gb1, Gb2) employed for continuously injecting the same current I on the two nodes (A, B) of the lowpass filter may be controlled through a common mode feedback loop for enhanced precision.

Abstract translation: 采用通过交换控制的电流发生器可充电和放电的低通滤波器网络的差分电荷泵电路采用两个相同的电流发生器（Gb1，Gb2），以基本上连续的方式在两个有效节点上注入相同的电流I A，B）和分别连接到所述节点（A，B）的两对相同的开关控制电流发生器（Gc1，Gc2，Gc3，Gc4），每个都能够拉电流I.两个发生器 通过一对控制信号（UP，DOWN）和所述一对控制信号中的另一对的反相信号分别对所述两对中的每一个进行形成。 所有这四台交换式发电机可能是相同类型（N型），从而确保高速度和精度。 用于在低通滤波器的两个节点（A，B）上连续注入相同电流I的两个（P型）电流发生器（Gb1，Gb2）可以通过共模反馈回路来控制，以提高精度。

公开(公告)号：EP0763887A1

公开(公告)日：1997-03-19

申请号：EP95830377.8

申请日：1995-09-14

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l. ,  CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Bruccoleri, Melchiorre ,  Demicheli, Davide ,  Demicheli, Marco ,  Patti, Giuseppe

IPC: H03G1/00 ,  H03G3/20 ,  G11B5/02

CPC classification number: H03G3/3026 ,  G11B5/02 ,  H03G1/0088

Abstract: The circuit described comprises a double half-wave rectifier (DHWR) connected to the outputs of the differential amplifier (VGA) in order to produce two quantities dependent on the amplitudes of the half-waves of the output signal of the amplifier (VGA), two comparators (COMP1, COMP2) each having an input (IN+1, IN+2) connected to an output (OUT1, OUT2) of the rectifier (DHWR) and a reference input (IN-1, IN-2) in order to produce respective output signals when the amplitudes of the respective half-waves are greater than the levels applied to the reference inputs (IN-1, IN-2), and processing means (Str1, A1, R1, Str2, A2, R2, C) for generating a signal for regulating the gain of the amplifier in dependence on the durations of the output signals of the two comparators.
The circuit may advantageously be used when the signal to be amplified (v+, v-) is not symmetrical.

Abstract translation: 所描述的电路包括连接到差分放大器（VGA）的输出的双半波整流器（DHWR），以便产生取决于放大器（VGA）的输出信号的半波幅度的两个量， 每个具有连接到整流器（DHWR）的输出（OUT1，OUT2）和参考输入（IN-1，IN-2）的输入（IN + 1，IN + 2））的两个比较器（COMP1，COMP2） 当各个半波的振幅大于施加到参考输入（IN-1，IN-2）的电平时，产生相应的输出信号，并且处理装置（Str1，A1，R1，Str2，A2，R2， C），用于根据两个比较器的输出信号的持续时间产生用于调节放大器的增益的信号。 当待放大的信号（v +，v-）不对称时，可以有利地使用该电路。

公开(公告)号：EP0743758A1

公开(公告)日：1996-11-20

申请号：EP95830197.0

申请日：1995-05-15

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Bruccoleri, Melchiorre ,  Demicheli, Marco ,  Patti, Giuseppe ,  Pisati, Valerio

IPC: H03M1/00 ,  G06J1/00 ,  H03M1/78

CPC classification number: H03M1/664 ,  G06J1/00 ,  H03M1/785

Abstract: A digital/analog quadratic converter (DACQ) composed by a pair of linear converters connected in cascade has a direct coupling of the output node of the first converter (DAC1) with a node of a R-2R type resistive network of the second converter (DAC2) corresponding to the LSB stage of the R-2R type resistive network. High impedance nodes, notably the input node of the second linear converter, are advantageously eliminated from the "current path" thus markedly reducing the problems of relatively long settling times of high impedance nodes (having intrinsically large parasitic capacitances associated therewith). The peculiar architecture of the quadratic converter provides also for a remarkable simplification of the circuit.

Abstract translation: 由串联的一对线性转换器组成的数字/模拟二次转换器（DACQ）具有第一转换器（DAC1）的输出节点与第二转换器的R-2R型电阻网络的节点的直接耦合（ DAC2）对应于R-2R型电阻网络的LSB级。 高阻抗节点，特别是第二线性转换器的输入节点，有利地从“电流路径”中消除，从而显着地减少了高阻抗节点（具有与其相关的本质上大的寄生电容）的较长建立时间的问题。 二次转换器的独特结构也为电路的显着简化提供了依据。