公开(公告)号：EP0805556A1

公开(公告)日：1997-11-05

申请号：EP96830247.1

申请日：1996-04-30

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Maccarrone, Marco ,  Ghezzi, Stefano ,  Branchetti, Maurizio

IPC: H03K17/22

CPC classification number: H03K17/223

Abstract: The present invention relates to an electronic power on reset circuit (1) of the type comprising a comparator (2) having at least two inputs and one output (A) for receiving a first reference signal from a generator block (11) and a second signal proportional to a supply voltage (Vdd) from a divider block (12) and for producing at output an initialization signal (INTPOR). Advantageously the output (A) is connected to a third turn off enablement input (10) of the comparator (2) through the series of an inverter pair (I1,I2).
The generator block (11) and the divider block (12) also comprise respective turn off enablement inputs (15,13) connected downstream of the inverter pair (I1,I2).

Abstract translation: 本发明涉及一种电子上电复位电路（1），其类型包括具有至少两个输入的比较器（2）和一个用于从发电机组（11）接收第一参考信号的输出（A）和一个第二 信号与来自分频器块（12）的电源电压（Vdd）成比例，并用于在输出端产生初始化信号（INTPOR）。 有利地，输出（A）通过一系列逆变器对（I1，I2）连接到比较器（2）的第三关断使能输入端（10）。 发电机组（11）和分频器模块（12）还包括连接在逆变器对（I1，I2）下游的相应的关断使能输入端（15,13）。

公开(公告)号：EP0822660A1

公开(公告)日：1998-02-04

申请号：EP96830430.3

申请日：1996-07-31

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Campardo, Giovanni ,  Zanardi, Stefano ,  Branchetti, Maurizio

IPC: H03K17/00 ,  H01L27/092

CPC classification number: H01L27/0928

Abstract: A low-noise output stage (1) for electronic circuits (2) integrated on a semiconductor substrate (3) is disclosed which comprises a complementary CMOS transistor pair (Pu,Nu) of the P-channel pull-up and the N-channel pull-down type, respectively, connected across a first terminal (A) of the circuit receiving a supply voltage (Vdd), and a second terminal (D) of the circuit being held at a second reference potential (GND). The transistors are connected together to form an output terminal (U) for connection to an external load (Cload), and the pull-down transistor is formed in a three-well structure to prevent propagation of a discharge current (Id) from the external load through the substrate (3).

Abstract translation: 公开了一种集成在半导体衬底（3）上的用于电子电路（2）的低噪声输出级（1），其包括P沟道上拉和N沟道上的互补CMOS晶体管对（Pu，Nu） 分别连接在接收电源电压（Vdd）的电路的第一端子（A）和保持在第二参考电位（GND）的电路的第二端子（D）之间的下拉型。 晶体管连接在一起以形成用于连接到外部负载（Cload）的输出端子（U），并且下拉晶体管形成为三阱结构，以防止放电电流（Id）从外部传播 穿过基底（3）。

公开(公告)号：EP0855788A1

公开(公告)日：1998-07-29

申请号：EP97830014.3

申请日：1997-01-23

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Ghilardelli, Andrea ,  Mulatti, Jacopo ,  Branchetti, Maurizio

IPC: H02M3/07

CPC classification number: H02M3/073

Abstract: A negative charge pump circuit comprises a plurality of charge pump stages (S1'-S4') connected in series to each other. Each stage has a stage input terminal (SI) and a stage output terminal (SO). A first stage (S1') has the stage input terminal (SI) connected to a reference voltage, a final stage (S4') has the stage output terminal (SO) operatively connected to an output terminal (O) of the charge pump at which a negative voltage is developed; intermediate stages (S2' ,S3') have the respective stage input terminal (SI) connected to the stage output terminal (SO) of a preceding stage and the respective stage output terminal connected to the stage input terminal of a following stage. Each stage (S1'-S4') comprises a first N-channel MOSFET (M1') with a first electrode connected to the stage input terminal (SI) and a second electrode connected to the stage output terminal (SO), a second N-channel MOSFET (M2') with a first electrode connected to the stage output terminal (SO) and a second electrode connected to a gate electrode of the first N-channel MOSFET (M1'), a boost capacitor (CP) with one terminal connected to the gate electrode of the first N-channel MOSFET and a second terminal driven by a respective first digital signal (A',C') switching between the reference voltage and a positive voltage supply (VDD), and a second capacitor (CL) with one terminal connected to the charge pump stage output terminal (SO) and a second terminal connected to a respective second digital signal (B',D') switching between the reference voltage and the voltage supply (VDD). A gate electrode of the second N-channel MOSFET (M2') is connected, in the first stage (S1'), to a third digital signal (D') switching between the reference voltage and the voltage supply, while in the remaining stage the gate electrode of the second N-channel MOSFET is connected to the stage input terminal (SI).

Abstract translation: 负电荷泵电路包括彼此串联连接的多个电荷泵级（S1'-S4'）。 每个级具有级输入端（SI）和级输出端（SO）。 第一级（S1'）具有连接到参考电压的级输入端（S1），最后级（S4'）使级输出端（SO）可操作地连接到电荷泵的输出端（O） 开发出负电压; 中间级（S2'，S3'）具有连接到前一级的级输出端（SO）的各级输入端（SI）和连接到后级的级输入端的各级输出端。 每个级（S1'-S4'）包括第一N沟道MOSFET（M1'），其中第一电极连接到级输入端（SI），第二电极连接到级输出端（SO），第二N - 沟道MOSFET（M2'），第一电极连接到平台输出端子（SO），第二电极连接到第一N沟道MOSFET（M1'）的栅电极，升压电容器（CP） 连接到第一N沟道MOSFET的栅电极和由在基准电压和正电压源（VDD）之间切换的相应的第一数字信号（A'，C'）驱动的第二端子和第二电容器（CL ），一个端子连接到电荷泵级输出端子（SO），第二端子连接到在参考电压和电压源（VDD）之间切换的相应的第二数字信号（B'，D'）。 第二N沟道MOSFET（M2'）的栅电极在第一级（S1'）中连接到在参考电压和电压源之间切换的第三数字信号（D'），而在剩余级 第二N沟道MOSFET的栅电极连接到级输入端（SI）。

公开(公告)号：EP0843402A1

公开(公告)日：1998-05-20

申请号：EP96830581.3

申请日：1996-11-14

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Ghilardelli, Andrea ,  Mulatti, Jacopo ,  Branchetti, Maurizio

IPC: H02M3/07

CPC classification number: H02M3/073

Abstract: A charge pump comprises a plurality of stages (S1,S2,S3',S4') connected in series between a reference potential and an output terminal (O) of the charge pump. The plurality of stages comprises a first group of stages (S1,S2), proximate to the reference potential, and a second group of stages (S3',S4') proximate to the output terminal of the charge pump. Each stage of the first group comprising a pass-transistor (M1) with first and second terminals respectively connected to an input and an output of the stage, and a first capacitor (CL) with a first plate connected to the output of the stage and a second plate driven by a digital signal (B,D) switching between the reference voltage and a positive voltage (VDD); each stage of the second group comprising a junction diode (D) having a first electrode connected to an input of the stage and a second electrode connected to an output of the stage, and a second capacitor (CL') having a first plate connected to the output of the stage and a second plate driven by a digital signal (B',D') switching between the reference voltage and the voltage supply.

Abstract translation: 电荷泵包括串联连接在电荷泵的参考电位和输出端（O）之间的多个级（S1，S2，S3'，S4'）。 多个级包括靠近参考电位的第一级级（S1，S2）和靠近电荷泵的输出端的第二组级（S3'，S4'）。 第一组的每个级包括具有第一和第二端子的传输晶体管（M1），第一和第二端子分别连接到级的输入和输出端，第一电容器（CL）具有连接到级的输出的第一板， 由数字信号（B，D）驱动的第二板，在参考电压和正电压（VDD）之间切换; 第二组的每个级包括具有连接到级的输入的第一电极和连接到级的输出的第二电极的结二极管（D）和具有连接到级的输出的第二电容器（CL'），第二电容器 该级的输出和由在基准电压和电压源之间切换的数字信号（B'，D'）驱动的第二板。

公开(公告)号：EP0806771A1

公开(公告)日：1997-11-12

申请号：EP96830243.0

申请日：1996-04-30

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Maccarrone, Marco ,  Ghezzi, Stefano ,  Branchetti, Maurizio

IPC: G11C16/06 ,  G11C16/04

CPC classification number: G11C16/24 ,  G11C16/0433

Abstract: The present invention concerns a redundant UPROM cell (1) incorporating at least one memory element (P0) of the EPROM or flash type having a control terminal (CG) and a conduction terminal (X) to be biased, a register (2) with inverters connected to the memory element and MOS transistors (M1,M3) connecting said memory element (P0) with a reference low voltage power supply (Vdd). There is provided a precharge network (5) for the conduction terminal (X) of the flash cell and said network (5) incorporates a complementary pair of transistors (M4,M5). The second transistor (M5) of said pair (M4,M5) is a natural N-channel MOS type.
With the UPROM cell (1) is associated a circuit portion (10) for generating at output (U) a live signal (UPCH) to be applied to the control terminal of the second transistor (M5) with the portion (10) comprising a timing section (7) and a generation section (8) for said second live signal (UPCH).

Abstract translation: 本发明涉及一种冗余UPROM单元（1），其结合有EPROM或闪存类型的至少一个存储元件（P0），其具有控制端（CG）和要偏置的导通端（X），寄存器（2）具有 连接到存储元件的反相器和将所述存储元件（P0）与参考低电压电源（Vdd）连接的MOS晶体管（M1，M3）。 提供了一种用于闪存单元的导电端子（X）的预充电网络（5），并且所述网络（5）包含互补的一对晶体管（M4，M5）。 所述对（M4，M5）的第二晶体管（M5）是自然的N沟道MOS型。 与UPROM单元（1）相关联的电路部分（10）用于在输出（U）上产生要施加到第二晶体管（M5）的控制端的实时信号（UPCH），其中部分（10）包括 定时部分（7）和用于所述第二实时信号（UPCH）的生成部分（8）。

公开(公告)号：EP0797147A1

公开(公告)日：1997-09-24

申请号：EP96830136.6

申请日：1996-03-21

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Branchetti, Maurizio ,  Conci, Armando ,  Golla, Carla

IPC: G06F12/00 ,  G06F11/00

CPC classification number: G06F11/1068

Abstract: The invention relates to a method of recovering faulty non-volatile memories. This method can be applied to an electrically programmable semiconductor non-volatile memory device being set up as a multi-sectors memory matrix and including selection circuitry for selecting words or individual bytes of the memory. According to this method, the memory matrix is addressed by byte, rather than by memory word, by acting said selection circuitry, whenever the device fails an operation test. The use of a Hamming code of error correction to remedy malfunctions due to manufacture allows the method to be applied to those devices which fail their test and would otherwise be treated as rejects.

Abstract translation: 本发明涉及一种恢复有缺陷的非易失性存储器的方法。 该方法可以应用于被设置为多扇区存储器矩阵并且包括用于选择存储器的字或单个字节的选择电路的电可编程半导体非易失性存储器件。 根据这种方法，每当设备操作测试失败时，存储器矩阵通过执行所述选择电路而以字节而不是存储字寻址。 使用汉明错误纠正代码来纠正由于制造造成的故障，可以将该方法应用于那些未能通过测试的设备，否则将被视为拒绝。

公开(公告)号：EP0766174A1

公开(公告)日：1997-04-02

申请号：EP95830408.1

申请日：1995-09-29

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Branchetti, Maurizio ,  Golla, Carla ,  Campardo, Giovanni

IPC: G06F11/10

CPC classification number: G06F11/1008

Abstract: The present invention relates to a memory device of the type comprising:

at least one first (M1) and one second (M2) memory cell array for storage respectively of a first plurality of user data and a second plurality of error identification and correction data,
first (D1) and second (D2) decoding means connected respectively to the first (M1) and second (M2) memory cell array for selection and reading respectively of the first and second pluralities of data,
error identification means (L1) coupled to said first (D1) and second (D2) decoder means, and
error correction means (C1,C2,EN) operationally connected to said first (D1) and second (D2) decoder means and to said error identification means (L1), and characterized in that it comprises at least one logical control unit (L2) operationally connected to the second decoder means (D2), to error identification means (L1) and to the error correction means (C1,C2,EN) to enable said second decoder means (D2) and said error correction means (C1,C2,EN) if an error is detected by the error identification means (L1).

Abstract translation: 本发明涉及一种存储器件，其类型包括：用于分别存储第一多个用户数据和第二多个错误识别和校正数据的至少一个第一（M1）和一个第二（M2）存储单元阵列， 第一（D1）和第二（D2）解码装置分别连接到第一（M1）和第二（M2）存储单元阵列，用于分别选择和读取第一和第二多个数据，错误识别装置（L1）耦合到所述 第一（D1）和第二（D2）解码器装置以及可操作地连接到所述第一（D1）和第二（D2）解码器装置和所述错误识别装置（L1）的纠错装置（C1，C2，EN） 其特征在于，它包括至少一个逻辑控制单元（L2），可操作地连接到第二解码器装置（D2），错误识别装置（L1）和纠错装置（C1，C2，EN），以使所述第二解码装置 （D2）和所述误差校正装置（C 1，C2，EN），如果错误识别装置（L1）检测到错误。