公开(公告)号：EP0851485A1

公开(公告)日：1998-07-01

申请号：EP96830649.8

申请日：1996-12-24

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Camerlenghi, Emilio ,  Colabella, Elio ,  Pividori, Luca ,  Rebora, Adriana, SGS-Thomson Microelectronics Srl

IPC: H01L21/8247

CPC classification number: H01L27/11521 ,  H01L21/3213 ,  H01L21/76838

Abstract: Self-aligned etching process for providing a plurality of mutually parallel word lines in a first conducting layer (11,12) deposited over a planarized architecture (9) obtained starting from a semiconductor substrate (1) on which is provided a plurality of active elements extending along separate parallel lines e.g. memory cell bit lines (13) and comprising gate regions made up of a first conducting layer (4), an intermediate dielectric layer (5) and a second conducting layer (6) with said regions being insulated from each other by insulation regions (7,8) to form said architecture (9) with said word lines being defined photolithographically by protective strips implemented by means of:

a vertical profile etching for complete removal from the unprotected areas of the first conducting layer (11,12), of the second conducting layer (6) and of the intermediate dielectric layer (5) respectively, and
a following isotropic etching of the first conducting layer (4).

Abstract translation: 自对准蚀刻工艺，用于在沉积在由半导体衬底（1）开始的平坦化架构（9）上沉积的第一导电层（11,12）中提供多个相互平行的字线，其上设置有多个有源元件 沿着单独的平行线延伸，例如 存储单元位线（13），并且包括由第一导电层（4），中间介电层（5）和第二导电层（6）构成的栅极区域，所述区域由绝缘区域（7）彼此绝缘 ，8）以形成所述架构（9），其中所述字线由光刻地通过保护条定义，所述保护条通过以下方式实现：垂直轮廓刻蚀，用于从第一导电层（11,12）的未保护区域完全去除第二导电层 导电层（6）和中间介电层（5），以及对第一导电层（4）进行以下各向同性蚀刻。

公开(公告)号：EP0434121A1

公开(公告)日：1991-06-26

申请号：EP90203252.3

申请日：1990-12-11

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Camerlenghi, Emilio

IPC: H01L29/788 ,  H01L21/28 ,  H01L27/115

CPC classification number: H01L27/11517 ,  H01L27/115 ,  H01L29/7885

Abstract: The cell comprises a substrate (20) with diffusions of source (11) and drain (12) separated by a channel area (7, 8), a floating gate (4) superimposed over a first part of said channel area (8) and a control gate (10) formed by a first and a second polysilicon strip (4, 10), respectively, a cell gate oxide (3) between said floating gate (4) and said first part of the channel area (8), a transistor gate oxide (9') between said control gate (10) and a second part of the channel area (7), an interpoly oxide (9) between said floating gate (4) and said control gate (10) and a layer of dielectric filler (14). By means of a process which provides for self-aligned etchings of layers of polysilicon (4, 10, 15) and of oxides (3, 9, 9') there is obtained a floating gate (4) and a control gate (10) self-aligned with one another and with the diffusions of source (11) and drain (12), as well as with the first oxide (1).

Abstract translation: 该电池包括由一个信道的区域（7,8），一浮置栅极（4）叠加在所述信道区域的第一部分（8）和分离的衬底（20）与源极（11）和漏极（12）的扩散 由第一和第二多晶硅条（4,10）形成的控制栅（10），分别为一个单元栅氧化物（3）之间的所述浮置栅极（4）和所述沟道区域的第一部分（8），一个 所述控制栅极（10）和沟道区的第二部分之间的晶体管栅极氧化物（9“）（7）间（interpoly）环氧乙烷（9）之间的所述浮置栅（4）与所述控制栅极（10）和层 电介质填充物（14）。 通过一种方法，其提供对多晶硅的层的自对准蚀刻（4,10，15）和氧化物的装置（3，9,9“）可以得到一种浮置栅极（4）和一控制栅极（10） 自对准彼此之间以及与源（11）和漏极（12）的扩散，以及与所述第一氧化物（1）。

公开(公告)号：EP0851426A3

公开(公告)日：1999-11-24

申请号：EP97830238.8

申请日：1997-05-23

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Camerlenghi, Emilio ,  Cappelletti, Paolo ,  Pividori, Luca

IPC: G11C7/00 ,  G11C16/04 ,  H01L21/8247

CPC classification number: H01L27/11521 ,  G11C7/18 ,  G11C8/12 ,  G11C16/0491 ,  H01L27/115

Abstract: An electronic memory device organized into sections which are in turn divided into blocks (1) formed of cells (3) and their associated decoding and addressing circuits (2), the cells being connected in a predetermined circuit configuration and each block being included between two opposite contact regions (4) which are interconnected by parallel continuous conduction lines referred to as the bit lines (7) . In the present invention, at least one interruption is provided in each bit line (7) near a contact region (4) by inserting a controlled switch (9) which functions as a block selector (8). Advantageously, the proposed solution allows each block to be isolated individually by enabling or disabling as appropriate the switches (9) of the cascade connected blocks (1). Also provided is a method of implementing the memory block (1), as organized into a matrix-like configuration, individually selectable from a plurality of blocks embedded in a memory device, wherein each memory cell (3) is identified by a continuous bit line (7) enabled by at least one block selector (8), by a broken bit line or 'segment' (13) connected to the continuous one (7) through an address device (2), and by a word line orthogonal to the direction of the bit lines, and formed on a substrate having a first type fo conductivity.

公开(公告)号：EP0851426A2

公开(公告)日：1998-07-01

申请号：EP97830238.8

申请日：1997-05-23

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Camerlenghi, Emilio ,  Cappelletti, Paolo ,  Pividori, Luca

IPC: G11C7/00 ,  G11C16/04 ,  H01L21/8247

CPC classification number: H01L27/11521 ,  G11C7/18 ,  G11C8/12 ,  G11C16/0491 ,  H01L27/115

Abstract: An electronic memory device organized into sections which are in turn divided into blocks (1) formed of cells (3) and their associated decoding and addressing circuits (2), the cells being connected in a predetermined circuit configuration and each block being included between two opposite contact regions (4) which are interconnected by parallel continuous conduction lines referred to as the bit lines (7) . In the present invention, at least one interruption is provided in each bit line (7) near a contact region (4) by inserting a controlled switch (9) which functions as a block selector (8).
Advantageously, the proposed solution allows each block to be isolated individually by enabling or disabling as appropriate the switches (9) of the cascade connected blocks (1).
Also provided is a method of implementing the memory block (1), as organized into a matrix-like configuration, individually selectable from a plurality of blocks embedded in a memory device, wherein each memory cell (3) is identified by a continuous bit line (7) enabled by at least one block selector (8), by a broken bit line or 'segment' (13) connected to the continuous one (7) through an address device (2), and by a word line orthogonal to the direction of the bit lines, and formed on a substrate having a first type fo conductivity.

Abstract translation: 组织成其又分为块部分电子存储装置（1）形成的单元（3）和它们的相关联的解码和处理电路（2），被包括两者之间被连接在规定的电路配置中的细胞，并且每个块 哪些是由被称为位线（7）平行的连续导线互连相对的接触区（4）。 （9）其功能是作为一个选择器块（8）在本发明中，至少一个中断，在每个位线（7）的接触区（4）附近通过将受控开关提供。 有利的是，提出的解决方案允许每个块单独地通过启用或禁用适当地隔离开关（9）的级联连接的模块（1）。 这样提供了一种实施存储块（1）中，作为组织成矩阵状的结构中，从嵌入在存储装置中的块的多个可单独选择，worin每个存储单元（3）的鉴定通过连续位线的方法 （7）通过至少一个块选择器（8）使能时，通过在地址装置（2）连接到连续一个（7）一个破碎位线或“段”（13），和由字线正交的 位线的方向，并且形成在具有第一导电类型FO一个基材。

公开(公告)号：EP0661715A1

公开(公告)日：1995-07-05

申请号：EP93830542.2

申请日：1993-12-31

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Casagrande, Giulio, c/o SGS-Thomson Micr.srl. ,  Camerlenghi, Emilio

IPC: G11C16/06 ,  G11C5/14

CPC classification number: G11C16/30 ,  G11C5/147

Abstract: A voltage regulator for electrically programmable non-volatile semiconductor memory devices of the type comprising a gain stage (3), supplied by a programming voltage (Vpp) and having an input terminal connected to a divider (6) of said programming voltage (Vpp) and an output terminal (U) connected to a programming line (5) of at least one memory cell (2) comprises at least one circuit element (4) capable of adapting the line programming voltage (5) to the length (L) of the memory cell (2).
This solution makes it possible to have on the bit line of the memory device a drain voltage varying according to the actual length of the memory cell.

Abstract translation: 一种用于电可编程非易失性半导体存储器件的电压调节器，包括由编程电压（Vpp）提供并具有连接到所述编程电压（Vpp）的分压器（6）的输入端的增益级（3） 和连接到至少一个存储单元（2）的编程线（5）的输出端子（U）包括至少一个电路元件（4），其能够使线路编程电压（5）适应于 存储单元（2）。 该解决方案使得可以在存储器件的位线上具有根据存储器单元的实际长度而变化的漏极电压。

公开(公告)号：EP0294864A2

公开(公告)日：1988-12-14

申请号：EP88201012.7

申请日：1988-05-20

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Camerlenghi, Emilio ,  Caprara, Paolo ,  Crisenza, Giuseppe

IPC: H01L21/316 ,  H01L21/82 ,  H01L27/10 ,  H01L29/78 ,  G11C17/00

CPC classification number: H01L29/66825 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/31662 ,  H01L27/115 ,  H01L29/7885

Abstract: The process calls for deposit of channel doping (1) on a semiconductor substrate (20); on the channel doping zone (1) is overlaid gate oxide (3) in a thin film which is deposited between doped side zones (4) on which are overlain areas of field oxide (2). On the layer of gate oxide (3) are placed a first polysilicon layer (5), an intermediate dielectric layer (9) and a second polysilicon layer (12). Selected surfaces of said deposited layers and said gate oxide layer (3) are removed to form a source junction zone (17) and a drain junction zone (18). The cell thus prepared is subjected to a source and drain reoxidation phase in a dry environment at a temperature of approximately 900°C. Then the contact opening, metallization and passivation operations are performed.

Abstract translation: 该进程调用用于在半导体衬底沟道掺杂（1）的存（20）; 在沟道掺杂区（1）上，叠置（3）在薄膜栅极氧化物全部被掺杂侧区之间沉积（4）在其上的场氧化物的叠置的区域（2）。 在栅氧化物（3）的层中间电介质层（9）和第二多晶硅层（12）上放置在第一多晶硅层（5）。 所述沉积层和所述栅极氧化物层（3）的选择的表面被去除，以形成一源极结区（17）和漏极结区（18）。 由此制备的细胞在900℃的温度下经受源极和漏极相再氧化在干燥环境中大约然后接触开口，金属化和钝化的动作。

公开(公告)号：EP0851493A1

公开(公告)日：1998-07-01

申请号：EP96830655.5

申请日：1996-12-27

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Camerlenghi, Emilio ,  Caprara, Paolo ,  Fontana, Gabriella, c/o SGS-Thomson

IPC: H01L27/00 ,  H01L21/768

CPC classification number: H01L21/76897 ,  H01L21/76838 ,  H01L2924/3011

Abstract: The present invention relates to a process for creation of contacts (25) in semiconductor electronic devices and in particular on bit lines of non-volatile memories with cross-point structure comprising memory cell matrices in which the bit lines are parallel unbroken diffusion strips (12) extending along a column of the matrix with the contacts (25) being provided through associated contact apertures (24) defined through a dielectric layer (21) deposited over a contact region defined on a semiconductor substrate (11) at one end of the bit lines (12). The process calls for a step of implantation and following diffusion of contact areas (22) provided in the substrate (11) at opposite sides of each bit line (12) to be contacted to widen the area designed to receive the contacts (25).

Abstract translation: 本发明涉及一种用于在半导体电子器件中形成触点（25）的方法，特别是在具有交叉点结构的非易失性存储器的位线上形成包括存储单元矩阵的存储单元矩阵的过程，其中位线是平行的不间断扩散条（12 ），其中所述触点（25）通过相关联的接触孔（24）提供，所述触点（24）通过沉积在位于所述钻头的一端的半导体衬底（11）上的接触区域上的介电层（21） 线（12）。 该过程需要在每个位线（12）的相对侧处设置在衬底（11）中的接触区域（22）的扩散步骤，以便接触，以扩大设计成接收触点（25）的区域。

公开(公告)号：EP0686979A1

公开(公告)日：1995-12-13

申请号：EP94830283.1

申请日：1994-06-10

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Campardo, Giovanni ,  Camerlenghi, Emilio

IPC: G11C29/00 ,  G11C16/06 ,  G06F11/20

CPC classification number: G11C29/82 ,  G06F2201/81 ,  G11C16/04 ,  G11C16/34 ,  G11C29/50 ,  G11C2029/5006

Abstract: Since fault phenomena such as lowering of the cell gain and cell emptying occur during normal operation the present invention proposes that in the memory device the row and/or column address decoding means (RDEC,CDEC) comprise at least one non-volatile memory (NVM) for address mapping and that the reading and writing control logic (CL) comprise means (TST) designed to identify cell faults in the rows and/or columns of the matrix (MAT) of the memory device and writing means (WM) designed to write on said non-volatile memory (NVM) during normal operation addresses corresponding to redundant rows and/or columns (RID) present in the matrix (MAT) to rectify said faults.

Abstract translation: 由于在正常操作期间发生诸如电池增益降低和电池排空之类的故障现象，本发明提出在存储器件中，行和/或列地址解码装置（RDEC，CDEC）包括至少一个非易失性存储器（NVM ），并且读和写控制逻辑（CL）包括被设计用于识别存储器件的矩阵（MAT）的行和/或列中的单元故障的装置（TST）和写入装置（WM），其被设计为 在对应于存在于矩阵（MAT）中的冗余行和/或列（RID）的正常操作地址期间在所述非易失性存储器（NVM）上写入以校正所述故障。

公开(公告)号：EP0661716A1

公开(公告)日：1995-07-05

申请号：EP93830543.0

申请日：1993-12-31

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Camerlenghi, Emilio ,  Casagrande, Giulio, c/o SGS-Thomson Micr.srl

IPC: G11C16/06 ,  G11C5/14

CPC classification number: G11C5/147 ,  G11C16/30

Abstract: A voltage regulator for electrically programmable non-volatile semiconductor memory devices of the type comprising a gain stage (3), supplied by a programming voltage (Vpp) and having an input terminal connected to a divider (6) of said programming voltage (Vpp) and an output terminal (U) connected to a programming line (5) of at least one memory cell (2) comprises at least one circuit element (4) capable of adapting the line programming voltage (5) to the length (L) of the memory cell (2).
This solution makes it possible to have on the bit line of the memory device a drain voltage varying according to the actual length of the memory cell.

Abstract translation: 一种用于电可编程非易失性半导体存储器件的电压调节器，包括由编程电压（Vpp）提供并具有连接到所述编程电压（Vpp）的分压器（6）的输入端的增益级（3） 和连接到至少一个存储单元（2）的编程线（5）的输出端子（U）包括至少一个电路元件（4），其能够使线路编程电压（5）适应于 存储单元（2）。 该解决方案使得可以在存储器件的位线上具有根据存储器单元的实际长度而变化的漏极电压。

公开(公告)号：EP0294864A3

公开(公告)日：1990-05-30

申请号：EP88201012.7

申请日：1988-05-20

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Camerlenghi, Emilio ,  Caprara, Paolo ,  Crisenza, Giuseppe

IPC: H01L21/316 ,  H01L21/82 ,  H01L27/10 ,  H01L29/78 ,  G11C17/00

CPC classification number: H01L29/66825 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/31662 ,  H01L27/115 ,  H01L29/7885

Abstract: The process calls for deposit of channel doping (1) on a semiconductor substrate (20); on the channel doping zone (1) is overlaid gate oxide (3) in a thin film which is deposited between doped side zones (4) on which are overlain areas of field oxide (2). On the layer of gate oxide (3) are placed a first polysilicon layer (5), an intermediate dielectric layer (9) and a second polysilicon layer (12). Selected surfaces of said deposited layers and said gate oxide layer (3) are removed to form a source junction zone (17) and a drain junction zone (18). The cell thus prepared is subjected to a source and drain reoxidation phase in a dry environment at a temperature of approximately 900°C. Then the contact opening, metallization and passivation operations are performed.