公开(公告)号：EP0811983A1

公开(公告)日：1997-12-10

申请号：EP96830333.9

申请日：1996-06-06

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Baldi, Livio ,  Maurelli, Alfonso ,  Marangon, Santina ,  Moroni, Maurizio

IPC: G11C11/34 ,  H01L27/115 ,  H01L21/8247

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11546

Abstract: The device includes flash-EEPROM memory cells (80), circuit transistors (81, 82) and high-voltage transistors (83, 84); and a layer of salicide, i.e. self-aligned titanium silicide, is formed on and contacting the source and drain regions of the cells (80) and transistors (81-84) and on and contacting the control gate regions of the cells and the gate regions of the transistors. The salicide, which reduces the series resistance of the transistors and so improves performance of the circuit portion, in no way impairs the electric characteristics, reliability or cycling characteristics of the cells, thus enabling the formation of mixed devices with a high-performance logic portion and a high storage capacity.

Abstract translation: 该装置包括快闪EEPROM的存储单元（80），电路晶体管（81，82）和高电压晶体管（83，84）; 自对准硅化物和的层，即 自对准硅化钛，是形成在与接触的细胞（80）和晶体管（81-84），而位于该源和漏区和接触细胞与所述晶体管的栅极区的控制栅的区域。 自对准硅化物，这降低了晶体管的串联电阻，因此改进了电路部分的性能，不以任何方式损害电池的电特性，可靠性或循环特性，从而使混合装置具有高性能逻辑部分形成 和高的存储容量。