-
公开(公告)号:DE69935291T2
公开(公告)日:2007-11-22
申请号:DE69935291
申请日:1999-07-30
Applicant: SIEMENS AG , IBM
Inventor: BOGGS KARL E , LIN CHENTING , NEUTZEL JOACHIM F , PLOESSL ROBERT , RONAY MARIA , SCHNABEL FLORIAN , STEPHENS JEREMY K
IPC: H01L21/304 , H01L21/3105 , B24B37/013 , B24B49/12 , H01L21/306 , H01L21/66 , H01L23/544
Abstract: The method of polishing metal layers on wafers comprises the steps of: using a chemical-mechanical polisher (50) to polish the metal layers (32) to remove material therefrom, inspecting indicator areas on the wafer to determine an amount of material removed from said areas (80), and adjusting the operation of the chemical-mechanical polisher (50) in response to the inspection of the indicator areas (80). The indicator areas (80) may include macroblocks comprised of a multitude of individual blocks (82). The wafer may be inspected by optically identifying the polishing state of the blocks (82) in the macroblock (80). Additionally, the process may be automated for mass production. A feedback loop to the polisher can be formed where data from optical inspection of macroblocks on a polished wafer can be immediately fed back to the polisher in order to adjust process parameters.
-
公开(公告)号:JPH1174273A
公开(公告)日:1999-03-16
申请号:JP18059098
申请日:1998-06-26
Applicant: SIEMENS AG
Inventor: PLOESSL ROBERT
IPC: H01L21/3205 , H01L21/304 , H01L21/768 , H01L23/52
Abstract: PROBLEM TO BE SOLVED: To form a metal wiring of small-size in an insulator board by applying chemical metallic polishing technique by shaping a trench by etching a board provided with a first insulation layer, filling the trench with a second insulation layer, and thereafter planarizing it by chemical and mechanical polishing treatment. SOLUTION: A resist layer is removed, until a dielectric layer 12 is exposed, and an opening part 14 and a surface of the dielectric layer 12 are charged by covering the dielectric layer 12 with an insulation layer 15. A material which is different from the dielectric layer 12 can be used as a material of the insulation layer 15 satisfactorily, such as polycrystalline polysilicon, oxide and other insulation materials. Then, the insulation layer 15 is polished and removed by applying a chemical and mechanical polishing method, and a surface of the dielectric layer 12 is exposed. As a result, a plug 16 consisting of the insulation layer 15 remains in the opening part 14 and flat surfaces of the plug 16 and the dielectric layer 12 are formed. Chemical and mechanical polishing is continued for a short time, even after the dielectric layer 12 has been exposed, and surfaces 20, 21 of a top part are made flat, since a part 17 of a dielectric layer is over-polished.
-
公开(公告)号:JPH11177064A
公开(公告)日:1999-07-02
申请号:JP27846098
申请日:1998-09-30
Applicant: SIEMENS AG
Inventor: PLOESSL ROBERT , FLIENTER BERTRAND
IPC: H01L21/302 , H01L21/3065 , H01L21/308 , H01L21/318 , H01L21/334 , H01L21/8242 , H01L27/108
Abstract: PROBLEM TO BE SOLVED: To form a deep trench by filling a material into the trench and polishing so that an excessive amount of material can be eliminated for exposing a hard mask layer. SOLUTION: A pad stack layer 310 provided on a substrate 301 includes a pad oxide layer 312 and has a pad etching stop layer 214 on it. Then, a sufficiently dense and hard etching mask layer 316 is formed on it, and patterning is made to constitute a block 320 for covering the array region of the substrate for constituting a deep trench. Then, the mask layer 316 is partially eliminated and the ear of a mask layer at a relatively small height projects onto the pad mask at the edge of the array, poly is deposited to fill into the trench and the ear appears on the surface of a poly layer and the height is relatively small. Therefore, as a result of wet etching, the ear of poly projecting onto the surface of a nitride layer is generated but is eliminated by anisotropic etching, thus avoiding the attach of a pad nitride and improving yield.
-
公开(公告)号:JPH1158217A
公开(公告)日:1999-03-02
申请号:JP17945498
申请日:1998-06-26
Applicant: SIEMENS AG
Inventor: PLOESSL ROBERT
Abstract: PROBLEM TO BE SOLVED: To eliminate those of grains and splits from an abrasive cloth surface by having a vacuum source actively connected to an opening installed in a conditioning member. SOLUTION: A central passage 64 is extending in passing through a robot arm 68, and it is opened to a void formed by the underside of a body part 76, a conditioning member 80 and the surface of abrasive cloth 70. Two outer passages 62 and 66 communicate with both passages 72 and 74 installed in the body part 76 and an opening 78 installed in the coditioning member 80, respectively. A vacuum source is actively connected to the surface of the polishing cloth 70. Therefore, those of grains and splits produced by a conditioning process are eliminabled in the arrow direction from the abrasive cloth 70. In addition, a conditioning surface 82 makes up a seal on the surface of the abrasive cloth 70 so as to maintain a vacuum force and to make these splits and grains effectively eliminable in the case where this conditioning surface 82 of the conditioning member 80 conditions the surface of the abrasive cloth 70.
-
公开(公告)号:JPH11284141A
公开(公告)日:1999-10-15
申请号:JP37452698
申请日:1998-12-28
Applicant: SIEMENS AG
Inventor: FLIETNER BERTRAND , PLOESSL ROBERT , GSCHOEDERER MONIKA
IPC: H01L27/108 , H01L21/033 , H01L21/308 , H01L21/8242
Abstract: PROBLEM TO BE SOLVED: To reduce an erosion of a pad during manufacturing a semiconductor by a method wherein a pad stack is formed on a substrate, and a hard mask comprising a first hard mask, an etch stop layer and a second hard mask layer is formed on the pad stack. SOLUTION: On a substrate surface, a pad stack layer 310 comprising a pad oxide film layer 312 and a pad stop layer 314 is formed and further a pad stop layer 312 as a pad nitride is formed. A hard mask layer 315 has an etch stop 318 between a first hard mask 316 and a second hard mask 320. And, the first hard mask 316 and the second hard mask 320 are composed of a material having minuteness or stiffness which sufficiently endures a collision of ions by RIE during a deep trench formation. Further, the etch mask has a wet etch rate higher than the pad etch stop layer.
-
公开(公告)号:DE69935291D1
公开(公告)日:2007-04-12
申请号:DE69935291
申请日:1999-07-30
Applicant: SIEMENS AG , IBM
Inventor: BOGGS KARL E , LIN CHENTING , NEUTZEL JOACHIM F , PLOESSL ROBERT , RONAY MARIA , SCHNABEL FLORIAN , STEPHENS JEREMY K
IPC: H01L21/304 , H01L21/3105 , B24B37/013 , B24B49/12 , H01L21/306 , H01L21/66 , H01L23/544
Abstract: The method of polishing metal layers on wafers comprises the steps of: using a chemical-mechanical polisher (50) to polish the metal layers (32) to remove material therefrom, inspecting indicator areas on the wafer to determine an amount of material removed from said areas (80), and adjusting the operation of the chemical-mechanical polisher (50) in response to the inspection of the indicator areas (80). The indicator areas (80) may include macroblocks comprised of a multitude of individual blocks (82). The wafer may be inspected by optically identifying the polishing state of the blocks (82) in the macroblock (80). Additionally, the process may be automated for mass production. A feedback loop to the polisher can be formed where data from optical inspection of macroblocks on a polished wafer can be immediately fed back to the polisher in order to adjust process parameters.
-
公开(公告)号:DE69809012D1
公开(公告)日:2002-12-05
申请号:DE69809012
申请日:1998-08-20
Applicant: SIEMENS AG
Inventor: PLOESSL ROBERT , FLIENTER BERTRAND
IPC: H01L21/302 , H01L21/3065 , H01L21/308 , H01L21/318 , H01L21/334 , H01L21/8242 , H01L27/108 , H01L21/311
Abstract: Improved technique of forming trench capacitors without causing excessive erosion at the edges of the array region resulting from polishing. The erosion is reduced by providing a block mask to protect the array region while partially removing a portion of the hard mask used to etch the trenches in the field region. The partial etch equalizes the height of the hard mask in the array and field region after formation of the deep trenches by a reactive ion etch.
-
公开(公告)号:DE69803335D1
公开(公告)日:2002-02-28
申请号:DE69803335
申请日:1998-05-29
Applicant: SIEMENS AG
Inventor: PLOESSL ROBERT
IPC: H01L21/3205 , H01L21/304 , H01L21/768 , H01L23/52
Abstract: A method of forming very small diameter metal lines in a substrate comprising forming an opening in a substrate using photolithographic techniques, filling the opening with a dielectric material and planarizing the substrate using chemical metal polishing techniques, which are continued so as to form small trenches on either side of the dielectric material, filling in the trenches with metal and planarizing the metal layer using chemical metal polishing.
-
公开(公告)号:DE69803335T2
公开(公告)日:2002-09-19
申请号:DE69803335
申请日:1998-05-29
Applicant: SIEMENS AG
Inventor: PLOESSL ROBERT
IPC: H01L21/3205 , H01L21/304 , H01L21/768 , H01L23/52
Abstract: A method of forming very small diameter metal lines in a substrate comprising forming an opening in a substrate using photolithographic techniques, filling the opening with a dielectric material and planarizing the substrate using chemical metal polishing techniques, which are continued so as to form small trenches on either side of the dielectric material, filling in the trenches with metal and planarizing the metal layer using chemical metal polishing.
-
公开(公告)号:HK1015544A1
公开(公告)日:1999-10-15
申请号:HK99100572
申请日:1999-02-11
Applicant: SIEMENS AG
Inventor: PLOESSL ROBERT
IPC: H01L21/3205 , H01L21/304 , H01L21/768 , H01L23/52 , H01L
Abstract: A method of forming very small diameter metal lines in a substrate comprising forming an opening in a substrate using photolithographic techniques, filling the opening with a dielectric material and planarizing the substrate using chemical metal polishing techniques, which are continued so as to form small trenches on either side of the dielectric material, filling in the trenches with metal and planarizing the metal layer using chemical metal polishing.
-
-
-
-
-
-
-
-
-